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TOSHIBA 



TLCS-9000/1 6 

INSTRUCTION SET MANUAL 

Version 2.2 



10 Feb 1994 



TOSHIBA CORPORATION 




B Byte (8 bits) 

W Word (16 bits) 

D Double word (32 bits) 

SS Operation size (0: word, 1: doubleword) 

SI - S0 Operation size (01: byte, 10: word, 11: doubleword) 

# Immediate data 
#4 4-bit immediate data 
#8 8-bit immediate data 
#16 16-bit immediate data 
#32 32-bit immediate data 

dst Destination for data transfer or operation result store 

Also, depending on the instruction, may mean source for operation data. When 
more than one, expressed as dstl, dst2.... 

src Source for transfer data or operation data. 

When more than one, expressed as srcl, src2.... 

num Source for numerical data. 

When more than one, expressed as nuxnl, num2.... 

abs Absolute operand address. Bit size may be denoted explicitly as absl3. 

disp Displacement. Bit size may be denoted explicitly as disp9 or displ3. 

Z,S,V,C Zero flag, Sign flag, Overflow flag. Carry flag 

@ Operation size. B: byte, W: word, D: doubleword 

Reg General-purpose registers R0 to R15 

SEA Short addressing mode 

LEA Long addressing mode 

MEM Effective address value 




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TLCS-9000 INSTRUCTION SET MANUAL 



R<3 : 0> 


General-purpose register 


T<3:0> 


General-purpose register 


M<7 :0> 


Long addressing mode 


N<7 : 0> 


Long addressing mode 


m<5 :0> 


Short addressing mode 


D<12:1> 


Displacement value. Sign-extended for use. 


D<8: 1> 


Displacement value. Sign-extended for use. 


A<12 : 0> 


Absolute address. Sign-extended for use. 


DD 


Indicates store direction. 

- In G format, 

0: register indicated by R<3:0>,1:address specified bym<5:0>. 

- In A format, 

0: address indicated by :A<12:0>,1 :address specified bym<5:0>. 


II 


Indicates the meaning of source field (M<7:0>) in G format. 
0: immediate data (8 bits, signed) 

1 : data specified by long addressing mode 


B<2:0> 


Bit number 


S<A:0> 


Offset value of bit to be operated on. (Used in bit field instruction) 


W<3:0> 


Width of bit to be operated on. (Used in bit field instruction) 


C<3:0> 


Type of condition to be tested for in conditional jump or conditional loop (jump non 
zero) instruction. 


V<3:0> 


Vector value (Used in software interrupt instruction) 



When the operation size is double word, odd numbered registers cannot be specified. 
RBn, RWn, and RDn are byte, word, and double word general-purpose registers respectively. 



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Flaq Changes 




Reset to 0. 



Set to 1. 



No change. 



Changes according to operation result. 
Indeterminate value. 





When flags change according to the result of an operation, they generally follow the 
rules described below. Exceptions to the rules are described later for each instruction. 




Zero flag. 

Set to 1 when the operation results in zero; otherwise, set to 0. 

Sign flag. 

The most significant bit (MSB) of the operation result is copied. 

Overflow flag. 

Set to 1 when an overflow occurs as a result of the operation; otherwise, set to 0. 
Carry flag. 

Set to 1 when a carry or borrow from the MSB occurs as a result of the operation; 
otherwise, set to 0. 



When a flag register is the target of an operation, the register is updated according to 
the result of the operation. In this case, updating using the operation result takes 
precedence over the above rule. 

(Example) ADD.B cc,1 Adds 1 to the value in the CC register (flag). The result (CC 

register value + 1) is set in the flag register. 



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Instruction formats 

Most instructions have multiple instruction formats for enabling various 
combinations of operands. Addressing modes for operands to be specified and 
combinations of modes differ depending on the instruction format. Instruction length 
and instruction execution time may differ, too. 

The programmer need not specify instruction formats because the assembler 
automatically selects appropriate formats. 

However, if desired, the programmer may specify a specific format. In such cases, add 
a colon and the name of a format, for example, : G to the end of the instruction 
mnemonic. 



S format 


Abbreviated type 

The types of operands which can be specified are restricted. 

However, this format is useful for minimizing the number of execution 
clocks and maximizing the efficiency of the object code. 


G format 


General binomial operation type 

General format for instructions which need two operands. 

Operands can be specified freely to provide powerful instruction functions. 


1 format 


Immediate type 

Useful for speeding up execution and maximizing the efficiency of object 
code for frequently used instructions which need an immediate 
data for source operands. If the operation size is double word, immediate 
data are allocated in the order, lower word followed by upper word. 




A format 


Absolute binomial operation type 

Useful for speeding up execution and maximizing the efficiency of object 
code for instructions which need two operands, one of which is an 
absolute address. 



(Examples) 



ADD.D RD6 ,4 
ADD. D:G RD6 ,4 
ADD.D: I RD6,4 
ADD.W (RD2 ) ,RW7 
ADD.WiS (RD2),RW7 



Automatically generates a 1-word instruction code 
in S format. 

Unconditionally generates a 2-word instruction 
code in G format. 

Unconditionally generates a 3-word instruction 
code in I format. 

Automatically generates an instruction code in G 
format. 

Assemble error occurs due to inhibited addressing 
mode combination in S format. 






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Special register (Non-bank section) 




General-purpose register (Bank section) 



31 23 15 7 0 




(Note) RWO or RDO can be used as a user stack pointer (USP) only when task mode 
(TM)inPSW = 1. Otherwise, handled as general-purpose registers. 



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• PSW bits 





31 


30 


29 


28 


27 


26 


25 


24 


23 


22 


21 20 


19 


18 


17 


16 




PSW 


RA 


□ 


TM 


□ 


BS 




_ 






15 


14 


13 


12 


11 


10 


9 


8 


7 


6 5 


4 


3 


2 


1 


0 






E 


- 


— 


E 


E 


0 


□ 


0 


IM 


E 


0 


V 


□ 



” indicates an undefined (reserved) bit; 0 is read and data written in the bit is 
ignored. 

All bits are cleared to “0” by resetting. 

Bit 8 to 4 are the same as the IMC register referenced. 

Bit 3 to 0 are the same as the CC register referenced. 



RA 



TM 





SS 



Return address stack (1 bit) 

0: Return address is in memory stack. 

1: Return address is in bank specified by PBP-1. 

Task mode, used to identify stack (1 bit) 

0: Using interrupt stack pointer (ISP), i.e., interrupt handler 
1: Using user stack pointer (USP), i.e., general-purpose task 

Number of banks (2 bits) 

00: Four banks with 16 registers (default value at reset) 

01: Three banks with 12 registers 
10: Two banks with 8 registers 
11: One bank with 4 registers 

User stack pointer size (1 bit) 

0: 16 bits (sign-extended for use) 

1: 32 bits 

Can also be referenced as user stack pointer, interrupt stack pointer and 
frame pointer size. 

Single step (1 bit) 

0: Normal operation 

1: Requests an interrupt for single step. 



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El Enable interrupt (1 bit) 

0: Disables maskable interrupts. 

1: Enables maskable interrupt according to mask level. 

Can also be referenced as the interrupt mask control register (IMC) as well 
as processor status word (PSW). 

Automatically cleared at interrupt entry. 

IM maskable interrupt mask (4 bits) 



0000: Enables all maskable interrupts. 

1111: Disables all maskable interrupts . 

Can also be referenced as the IMC as well as PSW. 

Z Zero (set when the operation result is all 0s.) 

Can also be referenced as the condition code register (CC) as well as PSW. 

S Sign bit (the most significant bit of the operation result is copied.) 

Can also be referenced as the CC as well as PSW. 

V Overflow viewed as signed binary numeral. 

Can also be referenced as the CC as well as PSW. 

C Carry or borrow. 

Can also be referenced as the CC as well as PSW. 




©PC Program counter. 

Always allocated at an even numbered address, since instructions come in units of 
words. Thus, the least significant bit of the PC is 0. 

© USP ... User stack pointer. 

RW0 and RD0 is used as USP when task mode is 1; otherwise, handled as a 
general-purpose register. 

When USP consists of 16 bits, RW0 is used as USP; when 32 bits, RD0 (RW0 + 
RW1) is used. 

When the stack pointer consists of 16 bits, the unused upper bits are sign-extended 
for reading. Writing data to these bits are not accepted. USP is undefined by 
resetting. 

© ISP Interrupt stack pointer 

Used as ISP when task mode is 0. 

When the stack pointer consists of 16 bits, bits 0 to 15 are used as ISP; when 32 
bits, bits 0 to 31 are used. When the stack pointer consists of 16 bits, the unused 
upper bits are sign-extended for reading. Writing data to these bits are not 
accepted. ISP is undefined by resetting. 



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© CBP . . . Current bank pointer 

The current register bank number is set in this register. Writing to this register 
changes banks. 

The unused upper bits are zero-extended to be read. Writing to these bits are 
invalid. 

© PBP . . . Previous bank pointer 

The bank number of the previously used bank is set in this register when banks 
are changed by an interrupt. This is because the PC and processor status word (PSW) 
of the program interrupted are saved in the register bank area. Thus PBP indicates 
the bank position which holds the information for the return. 

The unused upper bits are zero-extended to be read. Writing to these bits are 
invalid. PBP is undefined by resetting. 

© PSW . . . Processor status word 

Data including the status of the processor such as interrupt mask control, task 
mode, and mode setting are set in this register. 

Undeterminate (reserved) bits are set to “0” when reading. Writing to these bits 
are invalid. All bits are cleared to “0” by resetting. 

© CC Condition code register 

Data the same as the CC bit in the PSW are set in this register. 

Used only when accessing flags indicating the operation result in the PSW. 

The unused upper bits are zero-extended to be read. Writing to these bits are 
invalid. 

© IMC . . . Interrupt mask control register 

Data the same as the IMC bit in the PSW are set in this register. 

Used only when accessing bits related to interrupt mask control in the PSW. 

The unused upper bits are zero-extended to be read. Writing to these bits are 
invalid. 



© FP Frame pointer 

Used when creating or deleting a stack frame. When the stack pointer consists of 
16 bits, RW2 is used as FP; when 32 bits, RD2 (combined RW2 and RW3) is used. FP 
is undefined by resetting. 

© General purpose register 



Undefined by resetting. 






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Data Organization TLCS-9000 core CPU data organization 

1. Bit organization of data 

The TLCS-9000 core CPU can handle 1-, 8- (byte), 16- (word), and 32-bit (double word) 
data in most instructions. It can also handle 4-bit data in BCD operation instructions or 
data of any size (up to 16 bits) in bit field instructions. 

Unsigned binary data are expressed as: bit number n = 2 n . For example, byte data 
are expressed as follows: 

2 7 • B 7 + 26 • Bg + 25 • B 5 + 2 4 • B 4 + 23 • B 3 + 22 • B 2 + 21 • Bi + 20 • Bq 



MSB LSB 

Bit number 76543210 
Binary code 10100111 
Decimal 167 
Hexadecimal A7H 

• 

Signed binary data uses the MSB as a sign bit. When MSB = 0, the sign is positive; 
when MSB = 1, it is negative. 

For example, byte data are expressed as follows: 



. -2 7 • B 7 + 2*> • Bg + 25 • B s + 2 4 • B4 + 23 • B3 + 2 2 • B2 + 2 1 • Bi + 20 • B 0 

MSB LSB 

Bit number 76543210 
Binary code 10100111 
Decimal - 89 



2. Data organization in general-purpose registers 

There are up to 16 byte registers, indicated by RB0 to RB15. They use the lower 8 bits 
of a word register. 



MSB LSB 

Bit number 7 6 5 4 3 2 1 0 

There are up to 16 word registers, indicated by RWO to RW15. 

Each word register contains the byte register as its lower 8 bits and can be used as the 
upper half or the lower half of the double word register. 

MSB LSB 

Bitnumber 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 

There are up to 8 double word registers, indicated by RD0 to RD14 (even numbers 
only). RDn uses RWn as the lower word and RW n + 1 as the upper word. 



* 



MSB 

Bitnumber 31 30 29 



LSB 

5 4 3 2 1 0 





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TLCS-9000 INSTRUCTION SET MANUAL 



3. Data organization in memory 

With the TLCS-9000 core CPU, memory is accessed in two ways: by instruction fetch 
or data access. Restrictions on data organization in memory differ depending on the 
access method. 

In an instruction fetch, the start address can only be accessed from an even numbered 
address, in units of words. Whereas, in a data access, the start address can be accessed 
from either an even or an odd numbered address, in units of bytes, words, or double 
words. From the point of memory access execution time, it is better to organize word or 
double word data starting from an even numbered address. 

An example of data organization in memory is shown below. 

Address 0 Data 

MSB LSB 

7 6 5 43210 (Bit number) 



Instruction code 


Even numbered address 
Odd numbered address 


□□□□□□□□ 

□□□□□□□□ 

• 




Byte data 


Address n 


• 

□□□□□□□□ 

• 




Word data 


Address n 


□□□□□□□□ 


(Lower byte) 




Address n + 1 


□□□□□□□□ 

• 


(Upper byte) 


Double word data 


Address n 
Address n + 1 
Address n + 2 


□□□□□□□□ 

□□□□□□□□ 

□□□□□□□□ 


(Byte on LSB side) 




Address n + 3 


□□□□□□□□ 


(Byte on MSB side) 



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Memory map 

16M-byte Memory /IO area (specified by 24 bits) 



Address 

000000H 



Memory/IO area 



000800H 



VBP 



FFFFFEH 

FFFFFFH 



Bank RAM 
(2KB) 



Free Address area 



Interrupt table 



Free Address area 



VBP (2B) 



Address specification bound by simple addressing 



Absolute addressing bound (4K bytes) 



Indirect addressing bound by word pointer (32K bytes) 



| Int errupt table up to 256 (2K bytes) 



Indirect addressing bound by word pointer (32K bytes) 



T 



±1 



Absolute addressing bound (4K bytes) 



1. Vector base pointer (VBP): Initial program counter value after CPU reset is set. Variable 

from 000000H in units of 2K bytes. 

2. An interrupt is allocated in the interrupt Table starting from an address specified by the 
VBP in units of 8 bytes. 



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Addressing modes 

TLCS-9000 Series has 14 Addressing Modes. These Addressing modes use one of the 
two addressing mode format, Short Addressing Mode (SEA) and Long Addressing Mode 
(LEA) . 

Effective Addressing Mode Categories. 



General Register Direct Mode 


RBn / RWn / RDn 


Special Register Direct Mode 


SP / ISP / PBP / CBP / PSW / IMC / CC 


Register Indirect Mode 


(RWn /RDn) 


Register Indirect with Displace ment Mode 


(RWn / RDn + disp 9/13/20/24) 


SP Indirect with Displacement Mode 


(SP + disp 7/9/20) 




PC Indirect with Displacement Mode 


(PC + disp 9/ 20) 


Bank Register Indirect with Displacement Mode 


(RWn / RDn X 8 + disp 9 / 20) \ 


Register Indirect with Scaled Index Mode 


(RWm / RDm + RWn / RDn X ss + disp 9 / 20) 
(RWn / RDn X ss + disp 9/20) 


PC Indirect with Scaled Index Mode 


(PC + RWn / RDn X ss + disp 9 / 20) 


SP Indirect with Scaled Index Mode 


(SP + RWn / RDn X ss + disp 9 / 20) 


Register Indirect with Postincrement Mode 


(RWn/ RDn + +) 


Register Indirect with Predecrement Mode 


( RWn /RDn) 


Absolute Addressing Mode 


(disp 9/ 13/ 20/ 24) 


Immediate Data 


imm 4/8/ 16/32 



Most instructions contain one or both of the following two addressing mode fields. 

In both addressing mode fields, complicated addressing modes or displacement can be 
specified using addressing mode extension words. 

When the displacement is larger than the addressing mode extension word, prefix is 

used for extension as necessary. 

In register indirect addressing mode, register data is handled as signed and used as a 
24-bit address. 

Address data used to specify the addressing mode in A format are also handled as 
signed and used as a 24-bit address. 

SEA: Short addressing mode (6 bits) 

OOrrrr : RBn / RWn / RDn Note: RDn can only specify an even numbered register. 

Olrrrr : ( RWn ) 

* lOrrrr : ( RWn + disp ) etc. 

lliiii : Quick-Imm(#4). Note: iiii indicates signed. 

* : an extension word is required. 

When rrrr=0000, constant 0 is used instead of RWO. 



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LEA: Long addressing mode (8 bits) 

-OOOOrrrr • RBn / RWn / RDn Note: RDn can only specify an even numbered register. 
-MOhrrr : ( RWn ) 

* UOlOrrrr -r- ( RWn + disp ) etc. 

ft OOllrrrr : Special-Reg 

( Irani., SP, ISP, ESP, PBP, CBP, PSW, IMC, CC ) 
rrrr = OOOO, 1100, 0001, 0011, 0101, 0111, 1001, 1011, 1110 
% QTGOrrrr : ( RWn ++ ) 

X OlOlrrrr : ( -- RWn ) ~~ 

& OTIOrrrO : ( RDn + disp ) Note: RDn can only specify an even numbered register. 

GllOrrrl : ( RDn ) Note: RDn can only specify an even numbered register. 

% OlTIrrrO ^ ( RDn ++ Note: RDn can only specify an even numbered register. 

% QlTi-rrrr" : ( — RDn ) Note: RDn can only specify an even numbered register, 

lddddddd J ( SP + ddddddd ) Note: ddddddd indicates unsigned. (Zero extension) 

* : an extension word is required. 

rrrr*0000, constant 0 is used instead of RWO. 

& : an extension word is required. 

rrr*000, constant 0 is used instead of RDO. 

a : I mm. Data can be added. 

1-or 2-word immediate data is used depending on the operation size. 

% : an address is incremented or decremented by one if in bytes, 2 if in words, and 

4 if in double words, depending on the operation size. 



Addressing mode extension word 



An addressing mode extension word is added to the basic portion of the addressing 
modes described above. 

The register specified by the bit pattern of the basic portion is represented by Base. 

.4, i D\ 

( RWn + Base * ss + ddddddddd ) 



Orrrrssddddddddd 
lOrrrssddddddddd 
1 lOrrssddddddddd 
1 1 lddddddddddddd 



( RDn + Base * ss + ddddddddd ) 

( SpcR + Base * ss + ddddddddd ) 
( Base + ddddddddddddd ) 



ss: Scale factor 1(00), 2(01), 4(10), or 8(11) where Brackets () contain bit patterns. 

ddd ddd : Displacement used after it is sign-extended. 

RDn: Can only specify an even numbered register. 

SpcR: Constant^), PC, SP or (undefined and reserved) 
rr= tfoTlTflO, 01— 

A scale index is obtained by multiplying the register specified in Base by a scale 
factor (1/2/4/8) then adding the register contents and the displacement specified by the 
extension word to the result. 



Specifying constant 0 in Base results in PC relative, SP relative, or absolute. 

— % 



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Displacement extension (Prefix function) 

Displacements, which can be specified by addressing mode extension words, are 
either 9 or 13 bits and may not be long enough depending on the operand address. 

In such cases, allocating an instruction word which specifies a prefix before the bit 
pattern of the subject instruction enables a displacement extension (by inputting the 

excess bits from the upper bits in prefix). 

(Note) lddddddd in long addressing mode cannot be extended by a prefix. 

Instruction word 

NN = 0: prefix extension 0 (pfxO) 

= 1 : prefix extension 1 (pfxl) 

DIO D9 D8 D7 D6 D5 D4 D3 D2 D1 DO: Displacement data to be extended 




How pfxO and pfxl are used differs slightly depending on the instruction and operand 
as follows. 



Definition and usage of prefixes 

With the TLCS-9000 instruction set, two types of prefixes are used when the 
displacement size is not large enough. Usage differs as follows. 

An instruction can use both pfxO and pfxl simultaneously ; either can come first. 

Syntax: Operand with (0) can use pfxO if necessary. 

Operand with (1) can use pfxl if necessary. 



ABCD 


dst(l),src(0) 


ADC 


dst(l ) ,src(0) 


ADD 


dst(l),src(0) 


ADD 3 


dst,srcl(l ) ,src2(0) 


AND 


dst(l),src(0) 


ANDCF 


src( 1 ) ,num(0) 


BCHG 


dst(l),num(0) 


BFEX 


dst,src(l ) ,numl ,num2 


BFEXS 


dst , src( 1 ) ,numl ,num2 


BFIN 


dst ( 1 ) , src ,numl ,num2 


BRES 


dst(l ) ,num(0) 


BSOB 


dst(l ) ,src(0) 


BSOF 


dst(l),src(0) 



Add Decimal with Carry Flag 

Add with Carry Flag 

Add 

AddTrinominal 
Logical AND 

Bit Logical AND with Carry Flag 

1 Bit Inversion 

Extract Bit Field Unsigned 

Extract Bit Field Signed 

Bit Field Insert 

TBit Reset 

Bit Search for 0 Backward 
Bit Search for 0 Forward 




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BS1B 


dst( 1 ) ,src(0) 


Bit Search for 1 Backward 


BS1F 


dst ( 1 ) ,src(0) 


Bit Search for 1 Forward 


BSET ' 


dst( 1 ) ,num(0) 


1 Bit Set 


BTST 


src(l),num(0) 


Test 1 Bit 


CALL 


dst(O) 


Call Subroutine 


CALR 


disp(O) 


Call Subroutine Relative 


CBCD 


dst(l),src(0) 


Compare Decimal with Carry Flag 


CHK 


mem( 1 ) ,src(0) 


Check Bound Unsigned 


CHKS 


mem( 1 ) , src(O) 


Check Bound Signed 


CLR 


dst(O) 


Clear Operand 


CP 


dst( 1 ) , src(O) 


Compare 


CPC 


dst( 1 ) ,src(0) 


Compare with Carry Flag 


CPL 


dst(O) 


One's-Complement 


CPSN 


dst(l),src(0), cnts 


Compare String (Unmatch Detection) 


CPSZ 


dst(l),src(0),cnts 


Compare String (Match Detection) 


DIV 


dst(l),src(0) 


Unsigned Divide 


DIVS 


dst(l),src(0) 


Signed Divide 


DJNZC 


dst(0),cond,disp(l ) 


Decrement, Conditional and Jump Non-; 


DJNZ 


dst(0),disp(l) 


Decrement and Jump Non-zero 


EX 


dstl ( 1 ) ,dst2(0 ) 


Exchange 


EXTS 


dst(O) 


Sign Extend 


EXTZ 


dst(O) 


Zero Extend 


JP 


dst(O) 


Jump 


JRC 


cond,disp(0) 


Relative Jump Conditional 


JR 


disp(O) 


Relative Jump 


JRBC 


num,abs(l ) ,disp(0) 


Bit Test Relative Jump and Clear 


JRBS 


num,abs(l ) ,disp(0) 


Bit Test Relative Jump and Set 


LD 


dst( 1 ) ,src(0) 


Load 


LDA 


dst(l ) ,src(0) 


Load Effective Address 


LDCF 


src(l),num(0) 


Load Bit to Carry Flag 


LDS 


dst ( 1 ),src(0) , cnts 


Load String 


LINK 


disp(O) 


Link Stack Frame 


MAC 


dst,srcl(l ),src2(0) 


Unsigned Multiply-and-Add Calculation 


MACS 


dst ,srcl(l ) ,src2(0) 


Signed Multiply-and-Add Calculation 


MAX 


dst(l),src(0) 


Unsigned Maximum Value 


MAXS 


dst(l),src(0) 


Signed Maximum Value 


MIN 


dst(l),src(0) 


Unsigned Minimum Value 


MINS 


dst( 1 ) , src(O) 


Signed Minimum Value 


MIRR 


dst(O) 


Mirror Exchange 


MUL 


dst(l ) ,src(0) 


Unsigned Multiply 


MULS 


dst(l),src(0) 


Signed Multiply 


NEG 


dst(O) 


Negate 


OR 


dst( 1 ) , src(O) 


Logical OR 


ORCF - 


src(l) ,num(0) 


Bit Logical OR with Carry Flag 


POP 


dst(O) 


Pop from Stack 


PUSH 


src(O) 


Push to Stack 


PUSHA dst(O) 


Push Effective Address to Stack 


RETD 


disp(O) 


Return and Delete Parameter Area 


RL 


dst ( 1 ) ,num(0 ) 


Rotate Left with Carry Flag 


RLC 


dst(l),num(0) 


Rotate Left without Carry Flag 


RLM 


dstl ( 1 ) ,dst2 ,num(0) 


Rotate Left Multi Bit 






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RR dst( 1 ) ,num(0) 

RRC dst( 1 ) ,num(0) 

RRM dstl ( 1 ) ,dst2 ,num(0) 

RVBY dst(O) 

SBC dst( 1 ) ,src(0) 

SBCD dst ( 1 ) , src(0 ) 

SLA dst(l ) ,num(0) 

SLL dst(l ) ,num(0) 

SRA dst( 1 ) ,num(0) 

SRL dst( 1 ) ,num(0) 

STCF dst ( 1 ) ,num(0 ) 

SUB dst( 1 ) ,src(0) 

SUB3 dst,srcl(l ),src2(0) 
TJP dst(O) 

TSET dst(l),num(0) 

TST dst(O) 

XOR dst( 1 ) , src(O) 

XORCF src( 1 ) ,num(0) 



Rotate Right with Carry Flag 
Rotate Right without Carry Flag 
Rotate Right Multi Bit 
Reverse Byte 
Subtract with Carry Flag 
Subtract Decimal with Carry Flag 
Arithmetic Shift Left 
Logical Shift Left 
Arithmetic Shift Right 
Logical Shift Right 
Bit Transfer from Carry Flag (??) 
Subtract 

Subtract Trinominal 
Table Jump 
Test and Set 1 Bit 
Operand Test 
Exclusive OR 

Bit Exclusive OR with Carry Flag 



16 



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TLCS-9000 INSTRUCTION SET MANUAL 



Example of addressing mode field organization 

Below is an example of a typical addressing mode field organization. 



(Example) ADD. W (RW4+0EAh) ,RW7 ... S format 




1 0 
1 


0 


1 


0 


1 0 1 

I 1 


0 1 1 

1 1 


0 


0 10 0 
1 1 1 




1 1 
1 1 


1 


0 


0 


0 0 0 
1 1 1 1 


1 1 1 

1 1 1 1 


0 


10 10 
! 1 1 1 



Instruction word 



Extension word 



Point: Extension word can also be added to short addressing mode. 



(Example) ADD. w (SP+RW4*4+l234h),(SP+28h) ... G format 




\J 

Prefix 1 



Instruction word 1 



Instruction word 2 



Extension word 



Point: Prefix must be added before instruction word 1. 



17 









TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



(Example) ADD. w:G (RW4+12345h) , ( 10028h) ... G format 



110 10 


00000001000 


1 1 1 1 


1 1 1 1 1 1 1 1 1 1 



Prefix 0 



110 1 


1 


00000001001 


_J 1 1 


J 


1 1 1 1 -1 1 1 1 1 1 



Prefix 1 






1 0 


0 0 1 


1 1 1 


0 0 


1 0 0 0 0 0 


1 


1 1 


J 1 1 


1 


J 1 1 1 1 1 



Instruction word 1 



1 


1 1 


0000000101000 


[_ 


1 


1 1 1 1 1 1 1 1 1 J 1 1 



Extension word 



1 0 0 0 0 1 0 0 

1 1 1 1 1 1 


0 0 1 0 0 1 0 0 
1 1 1 1 1 1 1 




1 1 1 

1 1 


0001 101000101 
1 1 1 1 1 1 1 1 1 1 1 1 



Instruction word 2 



Point: Extension word must be added immediately afterthe basic portion of addressing 

mode. 

When constant 0 is specified in the addressing mode basic portion, absolute address 
is set. - * 



(Example) ADD. W (RW4+12345h),(10028h) ... A format 



110 10 


00000001000 


1 1 1 1 — 


1 1 1 1 1 1 1 — 1 — 1 — 1 — 



Prefix 0 






rr 


10 11 


00000001001 


L_^ 


1 1 1 


1 1 1 1 1 1 1 1 1 1 — 



Prefix 1 



1 0 


1 1 1 


1 0 


1 


10 0 0 


0 10 0 


1 


1 1 — 


1 




1 1 


1 1 1 



Instruction word 1 



1 


1 1 


0001 101000101 


L 


1 


1 1 1 1 1 1 1 1 1 1 1 1 — 



Extension word 



0 


0 0 


0000000101000 


L 


1 


1 1 1 1 1 1 1 1 1 1 — 1 — 1 — 



Instruction word 2 



Point: Total instruction word is 1 word shorter than the above example in G format. 



18 














TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



(Example) ADD. W:G (RW4+56h),3579h ... G format 



Instruction word 1 



Immediate data \J 



Instruction word 2 



Extension word 



Point: Extension word must be added immediately after the addressing mode basic 

portion. 




(Example) ADD. W (RW4+56h),3579h ... I format 



Instruction word 



Extension word 



001 1010101 1 1 1 0 0 1 I Immediate data 

I 1 1 I I I I I I I I I I I I I I 

Point: Total instruction word is 1 word shorter than the above example in G format. 

(Example) JRC NZ,S-1234h Prefix is added because disp is larger than 9 bits. 



Prefix 0 



Instruction word 

Point: Displacement is sign-extended after linked to prefix. $ symbol indicates PC relative . 




00000000 
J 1 1 1 I I l 




19 














TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



All instructions are listed below in alphabetical order. 
Detailed description for each of them follows. 



1 ABCD dst, src 

2 ADC dst, src 

3 ADD dst, src 

4 ADD 3 dst,srcl ,src2 

5 AND dst ,src 

6 ANDCF src,num 

7 BCHG dst,num 

8 BFEX dst , src ,numl , num2 

9 BFEXS dst , src ,numl ,num2 
10 BFIN dst ,src,numl ,num2 



11 BRES 

12 BSOB 

13 BSOF 

14 BS1B 

15 BS1F 

16 BSET 

17 BTST 

18 CALL 

19 CALR 

20 CBCD 

21 CCF 

22 CHK 

23 CHKS 

24 CLR 

25 CP 

26 CPC 

27 CPL 

28 CPSN 

29 CPSZ 

30 CSF 

31 CVF 

32 CZF 

33 DI 

34 DIV 

35 DIVS 

36 DJNZ 



dst,num 
dst, src 
dst, src 
dst, src 
dst, src 
dst,num 
src,num 
dst 
disp 
dst, src 

mem, src 
mem, src 
dst 

dst, src 
dst, src 
dst 

dst,src,conts 
dst, src, cents 



dst, src 
dst, src 
dst, disp 



37 DJNZC dst, cond, disp 



38 El. 

39 EX dstl ,dst2 

40 EXTS dst 

41 EXTZ dst 

42 HALT 

43 JP dst 



Add Decimal with Carry Flag 
Add with Carry Flag 
Add 

Add Trinominal 
Logical AND 

Bit Logical AND with Carry Flag 
Bit Change 

Extract Bit Field Unsigned 
Extract Bit Field Signed 
Bit Field Insert 
Bit Reset 

Bit Search for 0 Backward 
Bit Search for 0 Forward 
Bit Search for 1 Backward 
Bit Search for 1 Forward 
Bit Set 
Test Bit 

Call Subroutine 

Call Subroutine Relative 

Compare Decimal with Carry Flag 

Reverse Carry Flag 

Check Bound Unsigned 

Check Bound Signed 

Clear Operand 

Compare 

Compare with Carry Flag 

Ones-Complement 

Compare String (Unmatch detection) 

Compare String (Match detection) 

Invert Sign Flag 
Invert Overflow Flag 
Invert Zero Flag 
Disable Interrupt 
Unsigned Divide 
Signed Divide 

Decrement and Jump Non-zero 

Decrement, Conditional and Jump Non-zero 

Enable Interrupt 

Exchange 

Sign Extend 

Zero Extend 

Halt CPU 

Jump 



20 



TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



44 


JR 


disp 


45 


JRBC 


num,abs ,disp 


46 


JRBS 


num,abs ,disp 


47 


JRC 


cond,disp 


48 


LD 


dst , src 


49 


LDA 


dst , src 


50 


LDCF 


src ,nura 


51 


LDS 


dst ,src,cnts 


52 


LINK 


disp 


53 


MAC 


dst ,srcl ,src2 


54 


MACS 


dst,srcl,src2 


55 


MAX 


dst , src 


56 


MAXS 


dst , src 


57 


MIN 


dst , src 


58 


MINS 


dst , src 


59 


MIRR 


dst 


60 


MUL 


dst , src 


61 


MULS 


dst , src 


62 


NEG 


dst 


63 


NOP 




64 


OR 


dst , src 


65 


ORCF 


src,num 


66 


POP 


dst 


67 


PUSH 


src 


68 


PUSHA 


dst 


69 


RCF 




70 


RET 




71 


RETD 


disp 


72 


RET I 


• 


73 


RETS 




74 


RL 


dst ,num 


75 


RLC 


dst ,num 


76 


RLM 


dstl ,dst2,num 


77 


RR 


dst ,num 


78 


RRC 


dst ,num 


79 


RRM 


dstl ,dst2,num 


80 


RSF 




81 


RVBY 


dst 


82 


RVF 




83 


RZF 




84 


SBC 


dst ,src 


85 


SBCD 


ds t , src 


86 


SCF 




87 


SLA 


dst ,num 


88 


SLL 


dst ,num 


89 


SRA 


dst ,num 


90 


SRL 


dst ,num 


91 


SSF 




92 


STCF 


dst ,num 



Relative Jump 

BitTest Relative Jump and Clear 
Bit Test Relative Jump and Set 
Relative Jump Conditional 
Load 

Load Effective Address 
Load Bit to Carry Flag 
Load String 
Link Stack Frame 

Unsigned Multiply-and-Add Operation 

Signed Multiply-and-Add Operation 

Unsigned Maximum Value 

Signed Maximum Value 

Unsigned Minimum Value 

Signed Minimum Value 

Mirror Exchange 

Unsigned Multiply 

Signed Multiply 

Negate 

No Operation 

Logical OR 

Bit Logical OR with Carry Flag 
Pop from Stack 
Push to Stack 

Push Effective Address to Stack 

Reset Carry Flag 

Return 

Return and Delete Parameter Area 
Return from Interrupt 
Return from Single Step Interrupt 
Rotate Left with Carry Flag 
Rotate Left without Carry Flag 
Rotate Left Multi Bit 
Rotate Right with Carry Flag 
Rotate Right without Carry Flag 
Rotate Right Multi Bit 
Reset Sign Flag 
Reverse Byte 

Reset Overflow Flag Reset 
Reset Zero Flag 
Subtract with Carry Flag 
Subtract Decimal with Carry Flag 
Set Carry Flag 
Arithmetic Shift Left 
Logical Shift Left 
Arithmetic Shift Right 
Logical Shift Right 
Set Sign Flag 

Bit Transfer from Carry Flag 



21 



TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



93 


SUB 


dst , src 


94 


SUB3 


dst , srcl , src2 


95 


SVF 




96 


SWI 


vec 


97 


SZF 




98 


TJP 


dst 


99 


TSET 


dst ,num 


100 


TST 


dst 


101 


UNLK 




102 


XOR 


dst , src 


103 


XORCF 


src ,num 



1. List of Instruction Formats 



Instruction 


Addressing 


ABCD 


G,A 


ADC 


G,A 


ADD 


S,G,I,A 


ADD3 


AND 


S,G,I,A 


ANDCF 


G,A 


BCHG 


S ,G,A 


BFEX 

BFEXS 

BFIN 


BRES 


S,G,A 


BS0B 


G,A 


BS0F 


G,A 


BS1B 


G,A 


BS1F 


G,A 


BSET 


S,G,A 


BTST 


S,G,A 


CALL 

CALR 


CBCD 


G,A 


CCF 


CHK 


G,A 


CHKS 


G,A 


CLR 


CP 


S,G,I,A 


CPC. 


G,A 


CPL 

CPSN 

CPSZ 


CSF 


% 


CVF 

CZF 

DI 


DIV 


G,A 


DIVS 


G,A 



Subtract 

Subtract Trinominal 
Set Overflow Flag 
Software Interrupt 
Set Zero Flag 
Table Jump 
Test and Set Bit 
Operand Test 
Unlink Stack Frame 
Exclusive OR 

Bit Exclusive OR with Carry Flag 



Number of minimum instruction words 
2 
2 
2 
2 
1 
2 
1 
2 
2 
2 
1 
2 
2 
2 
2 
1 
1 
1 
1 
2 
1 
2 
2 
1 
1 
2 
1 
2 
2 
1 
1 
1 
1 
2 
2 



22 



TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



DJNZC 




2 


DJNZ 




2 


El 




1 


EX 


S,G,A 


1 


EXTS 




1 


EXTZ 




1 


HALT 




1 


JP 




1 


JRC 




1 


JR 




1 


JRBC 




2 


JRBS 




2 


LD 


S,G,I,A 


1 


LDA 




2 


LDCF 


G,A 


2 


LDS 




2 


LINK 




1 


MAC 




2 


MACS 




2 


MAX 


G,A 


2 


MAXS 


G,A 


2 


MIN 


G,A 


2 


MINS 


G,A 


2 


MIRR 




1 


MUL 


G,A 


2 


MULS 


G,A 


2 


NEG 




1 


NOP 




1 


OR 


S.G,I,A 


1 


ORCF 


G,A 


2 


POP 




1 


PUSH 




1 


PUSHA 




1 


RCF 




1 


RET 




1 


RETD 




1 


RETI 




1 


RETS 




1 


RL 


S,G,A 


1 


RLC 


S ,G, A 


1 


RLM 




2 


RR 


S ,G,A 


1 


RRO 


S ,G, A 


1 


RRM 




2 


RSF 




1 


RVBY 




1 


RVF 




1 


RZF 




1 


SBC 


G,A 


2 



23 



TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



SBCD 


G,A 


2 


SCF 




1 


SLA 


S,G,A 


1 


SLL 


S,G.A 


1 


SRA 


S ,G,A 


1 


SRL 


S,G,A 


1 


SSF 




1 


STCF 


G,A 


2 


SUB 


S,G,I ,A 


1 


SUB3 




2 


SVF 




1 


SWI 




1 


SZF 




1 


TJP 




1 


TSET 


G,A 


2 


TST 




1 


UNLK 




1 


XOR 


S,G,I,A 


1 


XORCF 


G,A 


2 


1 Format List 


ADD 


S,G,I,A 


i 


AND 


S»G f I, A 


i 


CP 


S,G,I ,A 


i 


LD 


S,G,I,A 


i 


OR 


S,G,I ,A 


i 


SUB 


S,G,I ,A 


i 


XOR 


S,G,I ,A 


i 


S Format List 


ADD 


S,G,I ,A 


i 


AND 


S,G,I,A 


i 


BCHG 


S ,G, A 


i 


BRES 


S,G,A 


i 


BSET 


S,G,A 


i 


BTST 


S,G,A 


i 


CP 


S , G , I , A 


i 


EX 


S,G,A 


i 


LD 


S,G,I,A 


i 


OR 


S,G,I ,A 


i 


RL . 


S ,G,A 


i 


RLC 


S,G,A 


i 


RR 


S,G,A 


i 


RRC 


S,G,A 


i 


SLA 


S,G,A 


i 


SLL 


S ,G,A 


i 


SRA 


S,G,A 


i 






24 



TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



SRL 


S,G,A 


1 


SUB 


S ,G,I ,A 


1 


XOR 


S,G,I,A 


1 


G Format List 


ABCD 


G,A 


2 


ADC 


G,A 


2 


ADD 


S,G,I,A 


1 


AND 


S,G,I,A 


1 


ANDCF 


G,A 


2 


BCHG 


S ,G,A 


1 


BRES 


S,G,A 


1 


BSOB 


G,A 


2 


BSOF 


G,A 


2 


BS1B 


G,A 


2 


BS1F 


G,A 


2 


BSET 


S,G,A 


1 


BTST 


S,G,A 


1 


CBCD 


G,A 


2 


CHK 


G,A 


2 


CHKS 


G,A 


2 


CP 


S,G,I,A 


1 


CPC 


G,A 


2 


DIV 


G,A 


2 


DIVS 


G,A 


2 


EX 


S,G,A 


1 


LD 


S,G,I,A 


1 


LDCF 


G,A 


2 


MAX 


G,A 


2 


MAXS 


G,A 


2 


MIN 


G,A 


2 


MINS 


G,A 


2 


MUL 


G,A 


2 


MULS 


G,A 


2 


OR 


S,G,I,A 


1 


ORCF 


G,A 


2 


RL 


S,G,A 


1 


RLC 


S,G,A 


1 


RR 


S,G,A 


1 


RRC 


S,G,A 


1 


SBC 


G,A 


2 


SBCD 


G,A 


2 


SLA 


S ,G,A 


1 


SLL 


S,G,A 


1 


SRA 


S,G,A 


1 


SRL 


S,G,A 


1 



25 




TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 




STCF 


G,A 


2 


SUB 


S,G,I ,A 


1 


TSET 


G,A 


2 


XOR 


S,G,I,A 


1 


XORCF 


G,A 


2 


Format List 


ABCD 


G,A 


2 


ADC 


G,A 


2 


ADD 


S,G,I ,A 


1 


AND 


S,G,I,A 


1 


ANDCF 


G, A 


2 


BCHG 


S,G,A 


1 


BRES 


S,G,A 


1 


BSOB 


G,A 


2 


BSOF 


G,A 


2 


BS1B 


G,A 


2 


BS1F 


G,A 


2 


BSET 


S,G,A 


1 


BTST 


S,G,A 


1 


CBCD 


G,A 


2 


CHK 


G,A 


2 


CHKS 


G,A 


2 


CP 


S,G,I,A 


2 


CPC 


G,A 


2 


DIV 


G,A 


2 


DIVS 


G,A 


2 


EX 


S,G,A 


1 


LD 


S,G,I,A 


1 


LDCF 


G,A 


2 


MAX 


G, A 


2 


MAXS 


G,A 


2 


MIN 


G,A 


2 


MINS 


G,A 


2 


MUL 


G,A 


2 


MULS 


G,A 


2 


OR 


S ,G,I , A 


1 


ORCF 


G, A 


2 


RL 


S,G,A 


1 


RLC 


S ,G, A 


1 


RR 


S,G,A 


1 


RRC 


S,G,A 


1 


SBC 


G,A 


2 


SBCD 


G,A 


2 


SLA 


S ,G, A 


1 


SLL 


S,G,A 


1 


SRA 


S ,G,A 


1 


SRL 


S,G,A 


1 


STCF 


G,A 


2 


SUB 


S,G,I,A 


1 




26 



TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



TSET G,A 2 

XOR S,G,I,A 1 

XORCF G,A 2 

6. Other Format List 

ADD3 2 

BFEX 2 

BFEXS 2 

BFIN 2 

CALL 1 

CALR 1 

CCF 1 

CLR 1 

CPL 1 

CPSN 2 

CPSZ 2 

CSF 1 

CVF 1 

CZF 1 

DJNZC 2 

DJNZ 2 

El 1 

EXTS ' 1 

EXTZ 1 

JP 1 

JRC 1 

JR 1 

JRBC 1 

JRBS 2 

HALT 1 

LDA 2 

LDS 2 

LINK 2 

MAC 1 

MACS 2 

MIRR 2 

NEG 1 

NOP 1 

POP 1 

PUSH 1 

PUSHA 1 

RCF 1 

RET 1 



27 





TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



RETD 

RETI 

RETS 

RLM 

RRM 

RSF 

RVBY 

RVF 

RZF 

SCF 

SSF 

SUB3 

SVF 

SWI 

SZF 

TJP 

TST 

UNLK 



1 

1 

1 

2 

2 

1 

1 

1 

1 

1 

1 

2 

1 

1 

1 

1 

1 

1 



7. Instructions Classified according to Operation 



Load 


CLR 




1 


LD 


S,G,I,A 


1 


LDA 




2 


POP 




1 


PUSH 




1 


PUSHA 




1 


Exchange 


EX 


S,G,A 


i 


MIRR 




i 


RVBY 




i 


Block load/block search 




CPSN 




2 


CPSZ 




2 


LDS 




2 


Arithmetic operation 




ABCD 


G,A 


2 


ADC 


G,A 


2 


ADD 


S,G,I,A 


2 


ADD3 




2 


CBCD 


G,A 


' 2 


CHK 


G,A 


2 


CHKS 


G,A 


2 


CP 


S,G,I,A 


1 


CPC 


G,A 


2 


DIV 


G,A 


2 


DIVS 


G,A 


2 


EXTS 




1 



28 




TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



EXTZ 




1 


MAC 




2 


MACS 




2 


MAX 


G,A 


2 


MAXS 


G,A 


2 


MIN 


G,A 


2 


MINS 


G,A 


2 


MUL 


G,A 


2 


MULS 


G,A 


2 


NEG 




1 


SBC 


G,A 


2 


SBCD 


G,A 


2 


SUB 


S,G,I,A 


1 


SUB3 




2 


TST 




1 


Logical operation 




AND 


S,G,I,A 


1 


CPL 




1 


OR 


S,G,I,A 


1 


XOR 


S,G, I ,A 


1 


Bit operation 


ANDCF 


G,A 


2 


BCHG 


S,G,A 


1 


BFEX 




2 


BFEXS 




2 


BFIN 




2 


BRES 


S ,G,A 


1 


BSOB 


G,A 


2 


BSOF 


G,A 


2 


BS1B 


G,A 


2 


BS1F 


G,A 


2 


BSET 


S,G,A 


1 


BTST 


S,G,A 


1 


CCF 




1 


CSF 




1 


CVF 




1 


CZF 




1 


LDCF 


G» A 


2 


ORCF 


G,A 


2 


RCF 




1 


RSF- 




1 


RVF 




1 


RZF 




1 


SCF 




1 


SSF 




1 


STCF 


G, A 


2 


SVF 




1 


SZF 




1 



29 





TOSHIBA 



TLCS-9000 instruction set manual 



TSET G,A 

XORCF G,A 



Special operation and CPU control 

DI 

El 



HALT 




LINK 




NOP 




SWI 




UNLK 




Rotate and shift 




RL 


S ,G , A 


RLC 


S ,G,A 


RLM 




RR 


S ,G, A 


RRC 


S,G,A 


RRM 




SLA 


S,G,A 


SLL 


S,G,A 


SRA 


S,G,A 


SRL 


S,G,A 



Jump, call, and return 

CALL 

CALR 

DJNZC 

DJNZ 

JP 

JRC 

JR 

JRBC 

JRBS 

RET 

RETD 

RETI 

RETS 

TJP 



2 

2 



1 

1 

1 

1 

1 

1 

1 



1 

1 

2 

1 

1 

2 

1 

1 

1 

1 



1 

1 

2 

2 

1 

1 

1 

2 

2 

1 

1 

1 

1 

1 




TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 




ABCD dst, src : Add Decimal with Carry Flag 




Operation : dst «- dst + src + C 

Description : Decimal-adds the contents of dst, src, and carry flag C, then loads the 

result in dst. 

Instruction format : 



G format : 

ABCD.@:G LEA, #8 
ABCD.@:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



si SO 0 0 II 1 1 1 M7 M6 M5 M4 M3 M2 


Ml ( M0 


1 0 0 1 0 1 0 0. N7 N6 N5N4N3N2, 

1 i l 1 1 1 1 1 J 1 1 1 1 1 1 


N1 NO 
| 



A format : 

ABCD.@:A MEM, SEA 
ABCD.@:A SEA, MEM 

When DD = 0, dst is memory specified by A<12:0> and src by m<5:0>. 
When DD = 1, dst and src are exchanged. 



SI | SO | ^ | 1 | 1 , m5 t m4 | 1 , DD , 0 [ 0 | 1 | m3 | m2 | ml | mO 
0 ( 0 | 0 A12A11 | A10 | A9 | A8 | A7 t A6 { A5 t A4 | A3 : A2 | A1 [ AO 



Flag status change : z S V C 




Operation size : 



B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 =11 (quick immediate) in A format allowed only when DD = 0. 

The Z flag is set to 1 when the Z flag = 1 and the operation result = 0; 
otherwise, cleared to zero. 

MSB of sign-extended immediate data must be “0”. If immediate data need to 
be sign-extended and its MSB is “1”, sign-extended bits are all Is, and data 
isn’t expressed in BCD. 

G format and II = 0 ; Byte operation — 00—99H 

Word or Double Word operation — 00~79H 
A format, DD = 0 and SEA = Quick Imm : 0~7 



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TLCS-9000 INSTRUCTION SET MANUAL 



ADC dst, src : Add with Carry Flag 




Operation : dst •*- dst + src + C 

Description : Adds the contents of dst and src and carry flag C, then loads the result 

in dst. 

Instruction format : 

G format : 

ADC.@:G LEA, #8 
ADC.@:G LEA, LEA 

M<7 : 0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 




A format : 

ADC.0:AMEM,SEA 
ADC. A SEA, MEM 



SI SO . 1 



1 mS m4 .1 DD 0 



0 m3 m2 ml mO 




0 0 A12.A1 1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO 



When DD = 0, dst is memory specified by A< 12:0> and src by m<5:0> 
When DD = 1, dst and src are exchanged. 



Flag status change : z S V C 




Operation size : b W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 =11 (quick immediate) in A format allowed only when DD = 0. 

The Z flag is set to 1 when the Z flag = 1 and the operation result = 0; 

otherwise, cleared to zero. 






TOSHIBA 



TLCS-9000 INSTRUCTlbN SET MANUAL 



ADD dst, src : Add 




Operation : dst <— dst + src 

Description : Adds the contents of dst and src, then loads the result in dst. 
Instruction format : 



S format : 

ADD.@:S Reg, SEA 
ADD.@:S SEA, Reg 



SI SO 0 RO 0 m5 m4 DD R3 R2 R1 0 m3 m2 ml mO 

I I I 1 I I I I I I I I I 1 1 

When DD = 0, dst is specified by R<3:0> and src by m<5:0> 

When DD = 1, dst and src are exchanged. 



G format : 

ADD.@:G LEA, #8 
ADD. 0:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



51 . 50 . 0 . 0 . " , 1 


1 1 M7 

L _1 1 


M6 

I 


M5 


M4 


M3 


M2 


Ml 


t MO 


1,0 0,0 0,1 


, 0 , 


0 N7 


N6 


. N5 


N4 


, N3 


, N2 


, N1 


NO 


1 


l l 


l 


J 


J 


J 


J 


J 


J 


j 



I format : 


0 0 
l 


. 0 . 0 , SS . 0 , 


0 0 M7 M6 M5 M4 M3 M2 Ml MO 


ADD. @ : I LEA, #16 
ADD . @ s I LEA, #32 


1 


1 I 1 1 1 


#<15:0> 

1 l l l l 1 1 1 1 


ji 


i 

i 

l L-. 


.L J. L i J. 


#<31:16> ! 

1 1 1 L...J 1 L— J 1 J 



M<7:0> = dst 



A format : 

ADD. @:A MEM, SEA 
• ADD.@:A SEA, MEM 

WhenDD = 0, dst is memory specified by A<12:0> and src by m<5:0>. 
WhenDD = 1, dst and src are exchanged. 



SI 


SO 1 

_L L_ _ 


. 1 1 1 . ms , m4 , 1 


, DD | 


0 


,° 


1° 


r 3 


m2 ml 


^ mO 


0 


, 0 


, 0 


A12 All A10 A9 , A8 


, A7 , 


A6 


, A5 


, A4 


, A3 




{ AO 




J 


J 


J 1 1 1 1 


J L 





J 


J 


J 



33 






TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



Flag status change : 




Operation size : b W D 




Notes : #< 31:16 > in I format is used when the operation size is double word. 

m5m4 =11 (quick immediate) and m5m4 = 00 (register direct) in S format 
allowed only when DD = 0. 

Immediate mode inhibited as dst addressing mode. 

m5m4 =11 (quick immediate) in A format allowed only when DD = 0. 





TOSHIBA 



V 



TLCS-9000 INSTRUCTION SET MANUAL 



ADD3 dst, srcl, src2 : Add Trinominal 




Operation : dst ■*— srcl + src2 

Description : Adds the contents of srcl and src2, then loads the result in dst. 
Instruction format : 



ADD3.0 Reg, LEA, #8 
ADD3.0 Reg, LEA, LEA 

M<7:0> = src2 When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = srcl, long addressing mode only 
R<3:0> = dst 



SI 


so 


0 


0 


II 1 1 1 


M7 


M6 


M5 


M4 


M3 


M2 Ml 


MO 




1 


1 


1 


1 1 1 1 


I 


1 


1 | 


1 I 




1 1 


1 


0 


R3 


| R2 


R1 


R0 0 0 0 


N7 


N6 


N5 


N4 


N3 


N2 N1 


NO 




J 




J 


J 1 1 1 


J 


J 


1 1 


1 L 




J 1 


1 



Flag status change : z S V C 




Operation size : b W D 




Notes : Immediate mode inhibited as srcl addressing mode. 



35 





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TLCS-9000 INSTRUCTION SET MANUAL 




Operation : dst *- dst AND src 

Description : ANDs the contents of dst and src, then loads the result in dst. 
Instruction format : 

S format : 

AND.@:SRegl,Reg2 

T<3:0> = dst 
R<3:0> = src 

G format : 

AND.@:G LEA, #8 
AND.@:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 





I format: 

AND .@:I LEA, #16 
AND.@:I LEA, #32 




M<7:0> = dst 



A format : 

AND. A MEM, SEA 
AND.@:A SEA, MEM 



SI . SO . 1 



1 m5 m4 1 DD . 1 0 ,0 m3 m2 ml mO 



0 | 0 | 0 A12 All A10 | A9 | A8 ( A7 | A6 | A5 ( A4 [ A3 | A2 t A1 ( AO 

When DD = 0, dst is memory specified by A<12:0> and src by m<5:0>. 
When DD = 1, dst and src are exchanged. 




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TLCS-9000 INSTRUCTION SET MANUAL 



Flag status change : z S V C 




Operation size 



B W D 




Notes : # < 31:16 > in I format is used when the operation size is double word. 

Immediate mode inhibited as dst addressing mode. 

m5m4 =11 (quick immediate) in A format allowed only when DD = 0. 



37 





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TLCS-9000 INSTRUCTION SET MANUAL 



ANDCF src. lium : Bit Logical AND with Carry Flacj 



vj 



Operation : C*-C AND src<num> 

Description : ANDs the contents of carry flag C with bit num of src, then loads the 

result in carry flag C. 

Instruction format : 



G format 



ANDCF. @:G LEA, #8 
ANDCF. @:G LEA, LEA 



SI SO 



M7 M6 M5 M4 M3 M2 Ml MO 




N7 N6 N5 N4N3.N2.N1 NO 




M<7:0> = num 



N<7:0 



When II = 0, immediate data (8 bits, signed) 
When II = 1, long addressing mode 
src, long addressing mode only 



A format 



ANDCF. A MEM, SEA 
ANDCF. @:A SEA, MEM 



SI SO 



1 m5.m4 1.DD1 



0 m3 m2 ml mO 




0 A12 A11.A10 A9 ,A8 A7A6 A5A4 A3 A2 A1 AO 



When DD = 0, src is memory specified by A<12:0> and num by m<5:0>. 
When DD = 1, num and src are exchanged. Ax 



Flag status change : z SVC Operation size : b W D 



Notes 




Immediate mode inhibited as dst addressing mode. 

m5m4 =11 (quick immediate) in A format allowed only when DD = 0. ' 

The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 



38 






TOSHIBA 



V 



TLCS-9000 INSTRUCTION SET MANUAL 



BCHG dst, num : Bit Change 




Operation : dst < num >■«- inverted value of dst < num > 
Description : Inverts the bit num value in dst. 

Instruction format : 



S format : 

BCHG.grS Reg, num 

In S format, the operation size is either byte or word. 

G format : 

BCHG.@:G LEA, #8 
BCHG.0:G LEA, LEA 



M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



51 l so , 0 , 0 , " . 1 , 1 , 1 , M7 , M6 , 


M5 


M4 M3 


M2 Ml MO 






N4 ( N3 ( 


N2 ( N1 ( NO 



S V°I ° I ’ I 1 . 1 . 1 I 1 ■ ° ,B' , B0.R3 ,R2 , R1 ,R0 

B<2:0> = num (When the operation size is word, num-8.) 

R<3:0> = dst 



A format : 

BCHG.@:A 
BCHG. 0: A 



MEM , SEA 
SEA, MEM 



When DD = 0, dst is memory specified by A<12:0> and num by m<5:0>. 
When DD = 1, dst and num are exchanged. 



SI , SO | 1 | ^ t 1 ,rn5 | m4 [ 1 | DD f 1 | 0 | 1 f m3 ( m2 | ml [ mO 
0 ( 1 t 0 A12An | A10 [ A9 | A8 ( A7 t A6 ( A5 ( A4 { A3 ( A2 | A1 | AO 



Flag status change : z S V C 




Operation size 



B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 =11 (quick immediate) in A format allowed only when DD = 0. 

The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 



39 








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TLCS-9000 INSTRUCTION SET MANUAL 



BFEX dst.src.num1.num2 : Extract Bit Field Unsigned 




Operation : dst <- src < numl + num2-l :numl> 

Description : Extracts the bit field specified by bit offset numl at address src and bit 

size num2, then loads the result without sign in register dst. 

Instruction format : 



BFEX.0 -Reg, LEA 

numl ,num2 

M<7:0> = src, long addressing mode only - 

R<3:0> = dst, register only 
P<3:0> = numl (bit offset) 

W<3:0> = num2 (bit size -1) 





Flag status change : z SVC Operation size : b W D 

_ I _ I ■ | _] I O I O I O I 

Notes : The operation size indicates the src operand size, dst always consists of 

words. 

The bit field is handled as unsigned. Thus, when bit size num2 is smaller 
than register dst, data is zero-extended then loaded in register dst. 

Immediate mode inhibited as src addressing mode. 

When the operation size is double word and the bit field corresponding to the 
upper word is to be operated on: 

- For registers, specify the value larger than the register number by 1 and 
execute in words. 

- For memory, specify the value larger than the normally specified address by 
2 and execute in words. 

To enable word execution, bit offset is restricted to 0 to 15. 

Write 1 to 16 in num2 in Assembler, then 0 to 15 obtained by decrementing 

by 1 is stored in the instruction codes. 

When the offset (numl) plus bit size (num2) exceeds the src operand size, the 
exceeded part is regarded as Os. 





TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



RFEXS dst, src, numl, num2 : Extract Bit Field Signed 




Operation : dst «— src < numl + num2 - 1 : numl > 

Description : Extracts the bit field specified by bit offset numl at address src and bit 

size num2, then loads the result with sign in register dst. 

Instruction format : 



BFEXS . @ Reg , LEA 

numl ,num2 



M<7:0> = src, long addressing mode only 
R<3:0> = dst, register only 
P<3:0> = numl (bit offset) 

W<3:0> = num2 (bit size -1) 



0 1110 


0 


SI 


so 


M7 


M6 


M5 


M4 


M3 M2 


Ml 


MO 


1 1 1 1 1 


1 


1 


J 






1 


1 


1 1 


J 


1 


0 R3 R2 R1 R0 


1 


0 


. P3 


P2 


PI 


, P0 


, 0 


W3 W2 


W1 


WO 


l 1 1 1 L 


1 


J 


1 


1 




J 


J 


J 1 


J 


J 



Flag status change : z S V C 




Operation size 



B W D 




Notes : The operation size indicates the src operand size, dst always consists of 

words. 

The bit field is handled as signed. Thus, when bit size num2 is smaller than 
register dst, data is sign-extended, then loaded in register dst. 

Immediate mode inhibited as src addressing mode. 

When the operation size is double word and the bit field corresponding to the 
upper word is to be operated on: 

- For registers, specify the value larger than the register number by 1 and 
execute in words. 

- For memory, specify the value larger than the normally specified address by 
2 and execute in words. 

To enable word execution, bit offset is restricted to 0 to 15. 

Write 1 to 16 in num2 in Assembler, then 0 to 15 obtained by subtracting 1 
from the num2 is stored in instruction codes. 

When the offset (numl) plus bit size (num2) exceeds the src operand size, the 
exceeded part is regarded as Os. 



41 






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TLCS-9000 INSTRUCTION SET MANUAL 



BFIN dst.src. numl, num2 : Bit Field Insert 



Operation : dst < numl + num2 — 1 : numl > *— src < num2 — 1 : 0 > 

Description : Loads the bit string specified by bit size num2 of register src in the bit 

field specified by bit offset numl and bit size num2 at address dst. 

Instruction format : 



BFIN.0 LEA, Reg 

numl ,num2 



0 SI SO M7 M6 M5 , M4 M3 M2 Ml MO 




M<7:0> = dst, long addressing mode only 
R<3:0> = src, register only 
P<3:0> = numl (bit offset) 

W<3:0> = num2 (bit size -1) 



Flag status change : z S V C Operation size : b W D 



Notes : The operation size indicates the dst operand size, src always consists of 

words. 

Immediate mode inhibited as src addressing mode. 

When the operation size is double word and the bit field corresponding to the 
upper word is to be operated on: 

- For registers, specify the value larger than the register number by 1 and 
execute in words. 

- For memory, specify the value larger than the normally specified address by 
2 and execute in words. 

To enable word execution, bit offset is restricted to 0 to 15. 

Write 1 to 16 in num2 in Assembler, then 0 to 15 obtained by subtracting 1 
from the written value is stored in instruction codes. 

When the offset (numl) plus bit size (num2) exceeds the dst operand size, the 
exceeded part is discarded and nothing remains in dst. 








42 








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TLCS-9000 INSTRUCTION SET MANUAL 



BRE S dst, num : Bit Reset 

NJ 



Operation : dst<num> <— 0 
Description : Resets bit num in dst. 
Instruction format : 



S format : 

BRES.@:S Reg, num 

B<2:0> = num (When the operation size is word, num-8.) 
R<3:0> = dst 

In S format, the operation size is either byte or word. 



G format : 

BRES.@:G LEA, #8 
BRES.0:G LEA, LEA 

M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



SI SO 0 0 II 1 1 1 M7 

1 1 1 1 1 1 1 1 1 


M6 M5 M4 M3 M2 Ml MO 
1 1 1 1 1 1 


1 1 0 1 0 1 0 0 N7 

1 1 1 1 1 1 1 l 


N6 N5 N4 N3 N2 N1 NO 

1 1 1 1 1 1 



S1 1 so i 0 1 1 1 0 1 1 1 1 1 1 1 0 1 ± 01 1 R3 1 R2 1 R1 1 R0 



A format : 

BRES.0JA 
BRES. 0: A 



MEM, SEA 
SEA, MEM 

WhenDD = 0, dst is memory specified by A<12:0> and num bym<5:0>. 
WhenDD = 1, dst and num are exchanged. 



SI 


I 50 . 1 


I 1 I 1 l m5 . m4 l 1 


|DD ( 1 


1° 


. 1 r 3 


I m2 


r 1 


! m0 


0 


, 0 


, o 


A12 All A10 A9 A8 


A7 A6 


, A5 


A4 A3 


, A2 


, A1 


AO 




J 


J 


J 1 1 1 1 


J 1 


J 


J 1 


J 


J 


J 



Flag status change : z S V C 




Operation size 



B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 =11 (quick immediate) in A format allowed only when DD = 0. 

The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 



43 







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TLCS-9000 INSTRUCTION SET MANUAL 



BSOB dst. src : Bit Search for 0 Backward 




Operation : dst «— operation result when searching src for the first 0 backward. 

Description : Searches the bit pattern of src for the first 0 backward (from MSB to 

LSB), then loads the number of bit where the first 0 is found in dst. 

Instruction format : 



G format : 

BS0B.@:G 

BS0B.@:G 



LEA , #8 
LEA, LEA 



SI | SO | 0 | 0 | II | 1 | 1 | 1 t M7 t M6 | M5 ( M4 | M3 t M2 | Ml | MD 
1 | 1 , Q , 1 | 1 [ 1 | 0 [ 0 t N7 | N6 t N5 | N4 | N3 t N2 t N1 [ NO 



M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



A format : 

BH0B.@: A MEM, SEA 
BS0B.@:A SEA, MEM 



SI SO 1 1 1 m5 m4 1 DD 1 0 1 m3 m2 ml mO 
1 0 0 A12A11A10 A9.A8 ,A7 ,A6 ,A5 ,A4 ,A3 ,A2 A1A0 



When DD = 0, dst is memory specified by A<12:0> and src by m<5:0>. 
When DD = 1, dst and src are exchanged. 



Flag status change : z S V C 




Operation size 



B W D 




Notes : If 0 was not found in the searched bit pattern, the contents of dst are set to 

indeterminate and the V flag is set to 1; otherwise, reset to 0. 

Immediate mode inhibited as dst addressing mode. 

m5m4 =11 (quick immediate) in A format allowed only when DD = 0. 





TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



BSOF dst, src : Bit Search for 0 Forward J 



Operation : dst <- operation result when searching src for the first 0 forward. 

Description : Searches the bit pattern of src for the first 0 forward (from LSB to MSB) 

and loads the number of bit where the first 0 is found in dst. 

Instruction format : 



G format : 

BS0F.@:G LEA, #8 
BS0F.@:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



S V°, 0 , 0 , " , 1 , 1 , 1 , M7 , M6 I 


M5 


M4 M3 M2 Ml 


M0 


1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 -I N7 I N6 I 




N4 ' N3 , N2 , N1 , 


NO 



A format : 

BS0F.@:A MEM, SEA 
BSOF. A SEA, MEM 

When DD = 0, dst is memory specified by A<12:0> and src by m<5:0>. 
When DD = 1, dst and src are exchanged. 



SI t SO | 1 t ^ | 1 t m5 | m4 | 1 | DD | 1 | 0 | 1 ^ m3 | m2 | ml f mO 
1,0,1 A12 All A10 | A9 ^ A8 | A7 | A6 | A5 | A4 [ A3 [ A2 | A1 f AO 



Flag status change : z S V C 



* 



Operation size 



• B W D 




Notes : If 0 was not found in the searched bit pattern, the contents of dst are set to 

indeterminate and the V flag is set to 1; otherwise, reset to 0. 

Immediate mode inhibited as dst addressing mode. 

m5m4 =11 (quick immediate) in A format allowed only when DD = 0. 



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TLCS-9000 INSTRUCTION SET MANUAL 




BS1B dst. src : Bit Search for 1 Backward 




Operation : dst <- operation result when searching src for the first 1 backward. 

Description : Searches the bit pattern of src for the first 1 backward (from MSB to 

LSB), then loads the number of bit where the first 1 is found in dst. 

Instruction format : 



G format : 

BS1B.0:G LEA, #8 
BS1B.@:G LEA, LEA 



A format : 

BS1B.@:A MEM, SEA 
BS1B.0SA SEA, MEM 

When DD = 0, dst is memory specified by A<12:0> and src by m<5:0>. 
WhenDD = 1, dst and src are exchanged. 



SI | SO | 1 t 1 | 1 | m5 | m4 f 1 | DD | 1 ,0 , 1 | m3 [ m2 | ml | mO 



1 [ 1 f 0 A12A11 A10 | A9 f A8 ( A7 | A6 [ A5 | A4 ( A3 | A2 ( A1 ( AO 



si i s °i° i 0 i - 1 



1 1 1 M7 M6 M5 M4 M3 M2 Ml MO 



1 1 0 1 1 1 1 0 N7 N6 N5N4 N3N2 N1 NO 

i l I I I I I I I 1 1 1 1 1 1 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



Flag status change : z S V C 




Operation size 



: B W D 




Notes : If 1 was not found in the searched bit pattern, the contents of dst are set to 

indeterminate and the V flag is set to 1; otherwise, reset to 0. 

Immediate mode inhibited as dst addressing mode. 

m5m4 =11 (quick immediate) in A format allowed only when DD = 0. 





TOSHIBA 



V- 

TLCS-9000 INSTRUCTION SET MANUAL 



BS1F dst, src : Bit Search for 1 Forward 



Operation : dst *— operation result when searching src for the first 1 forward. 

Description : Searches the bit pattern of src for the first 1 forward (from LSB to MSB), 

then loads the number of bit where the first 1 is found in dst. 

Instruction format : 



G format : 

BS1F.@:G LEA, #8 
BS1F.@:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



51 l so , 0 , 0 , 11 , 1 , 1 , ’ , M7 , M6 I 


M5 M4 M3 M2 Ml 


MO 


1 1 0 1 1 1 1 1 N7 N6 

1 1 1 1 1 1 


N5 N4 N3 N2 N1 
I 1 1 1 l 


NO 



A format : 

BS1F.@:A 

BS1F.@:a 



MEM, SEA 
SEA, MEM 

When DD = 0, dst is memory specified by A<12:0> and src by m<5:0>. 
When DD = 1, dst and src are exchanged. 



S1 . S0 . 1 , 1 . 1 1 


| DD | 1 


, ° 


1 1 I" 3 


l" 12 


I" 11 


| mO 


1,1,1 A12 All A10 A9 A8 


. A7 ,A6 


, A5 


A4 , A3 


, A2 


, A1 


| AO 





J 


J 


J 


J 


J 





Flag status change : z S V C Operation size 




B W D 




Notes : If 1 was not found in the searched bit pattern, the contents of dst are set to 

indeterminate and the V flag is set to 1; otherwise, reset to 0. 

Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 



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BSET dst, num : Bit Set 




Operation : dst<num> <— 1 
Description : Sets bit num in dst to 1. 
Instruction format : 



S format : 

BSET.@:S Reg, num . ... , n . 

B<2:0> = num (When the operation size is word, num-8.) 

R<3:0> = dst 

In S format, the operation size is either byte or word. 




G format : 

BSET . @ :G 
BSET.@:G 



LEA, #8 
LEA, LEA 



SI SO 



1 M7 M6 M5 M4 M3 M2 Ml MO 




1 N7 N6 N5.N4 N3.N2N1, NO 



M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



A format : 

BSET.@:A 

BSET.@:A 





SI 


l 50 l 


1,1,1 , mS , m4 , 1 


.DD. 1 


j_LuL 




i^i 


ill 


( mO 


MEM, SEA 
SEA, MEM 


0 


| 0 ( 


1 A12 All A10 | A9 ( A8 










i^l 





When DD = 0 , dst is memory specified by A<12:0> and num by m<5:0>. 
When DD = 1 , dst and num are exchanged. 



Flag status change : z S V C Operation size : b W D 



Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 =11 (quick immediate) in A format allowed only when DD = 0. 

The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 






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TLCS-9000 INSTRUCTION SET MANUAL 





Operation : Z *— inverted value of src < num > 

Description : Loads the inverted value of bit num of src in the Z flag. 
Instruction format : 

S format : 

BTST.@:S Reg, num 



G format : 

BTST.0:G LEA, #8 
BTST.@:G LEA, LEA 

M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = src, long addressing mode only 



SI SO , 0 1 1 1 1 1 1 B2 B1 BO R3 

I I I I I I I I I I I I 

B < 2 :0 > = num (When the operation size is word, num-8.) 

R<3:0> = src 

In S format, the operation size is either byte or word. 



SI SO . 0 . 0 . II 



1 M7 M6 M5 M4 M3 M2 Ml MO 



1 N7 N6 N5 N4 N3 N2 N1 NO 



A format : 

BTST.@:A MEM, SEA 
BTST.@:A SEA, MEM 

When DD = 0, dst is memory specified by A<12:0> and num by m<5:0>. 
WhenDD = 1, dst and num are exchanged. 




Flag status change : z S V C Operation size : b W D 



Notes : m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 











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TLCS-9000 INSTRUCTION SET MANUAL 



CALL dst : Call Subroutine 

Operation : SP «- SP - 4, (SP) «- PC, PC ■*- effective addresses of dst 

Description : Saves the contents of the program counter in the stack area and jumps 

to the dst effective address. 

Instruction format : 




CALL.0 LEA 

M<7:0> = dst 

Flag status change : z S V C Operation size : b W D 



Notes : SP «-SP- 4 is executed after the dst effective address is calculated. 

Register direct or immediate mode inhibited as dst addressing mode. 

The operation size is employed to increment or decrement an address by 
(RWn+ +), (~RWn), (RDn+ +) or (-RDn) in addressing mode. 

When the effective address of dst is odd numbered, jumps to an even 
numbered address obtained by rounding off the least significant bit to 0. 




1 ! SS ! 1 



1 



1 



1 M7 M6 M5 M4 M3 M2 Ml , MO 



i 






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TLCS-9000 INSTRUCTION SET MANUAL 



CALR disp : Call Subroutine Relative 



Operation : SP — SP -4, (SP) PC, PC «- PC + disp 



Description : Saves the contents of the program counter in the stack area and restarts 

the program from PC + disp. 



Instruction format : 



CALR disp 



0.0.1 D12.D11 DIO D9 . D8 . D7 D6 D5 D4 D3 D2 D1 1 



disp = D<12:0>, butsince always D<0> 
the instruction code. 



0, D<0> is not included in 



Flag status change : 



Z S V C 




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CBCD dst, src : Compare Decimal with Carry Flag 



Operation : dst - src - C 

Description : Decimal-subtracts the contents of src and carry flag C from the contents 

of dst, and reflects the result in condition code flag CC. 

Instruction format : 



G format : 

CBCD.@:G 

CBCD.@:G 



LEA, #8 
LEA, LEA 



S1 ■ S ° l ° . ° ■ 



1 1 1 M7M6M5 M4 M3 M2 Ml MO 

I I I I I I _J 1 1 1 1 



1 o 0 1 0 1 1 0 N7 N6 N5N4N3 N2 N1 NO 

llll I I I I J 1 1 1 1 1 1 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



A format : 

CBCD.@:A 

CBCD.@:A 



MEM, SEA 
SEA, MEM 



SI SO 1 



1 m5 m4 1 DD . 0 



1 m3 m2 ml . mO 




1 0 A12A11A10 A9 A8 A7 A6 ,A5 A4 A3 ,A2 A1 AO 



WhenDD = 0, dst is memory specified byA<12:0>and srcbym<5:0>. 
When DD = 1, dst and src are exchanged. 



Flag status change : z S V C 




Operation size : b W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

The Z flag is set to 1 when the Z flag = 1 and the operation result = 0; 
otherwise, cleared to zero. 

MSB of sign-extended immediate data must be “0”. If immediate data need to 
be sign-extended and its MSB is “1”, sign-extended bits are all Is, and data 
isn’t expressed in BCD. 

G format and 11=0 ; Byte operation - 00~99H 

Word or Double Word operation — 00~79H 

A format, DD = 0 and SEA = Quick Imm : 0~7 




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CCF : Complement of Carry Flag 

Operation : C «— inverted value of C 
Description : Inverts the contents of carry flag C. 
Instruction format : 




CCF 




Flag status change : z S V C 




53 




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TLCS-9000 instruction set manual 



CHK mpm. src : fhprk Unsigned Bound 




Operation : 



Description 



if src 2 (mem) (unsigned) then if src < (mem + size) then V - 0, C - 0 else 
V = 1,0 = 1 else V = 1,0=0 

: Checks without sign whether src is equal to or larger than (mem) and 

less than (mem + size). . 



src < (mem) 

(mem) ^ src < (mem + size) 
(mem + size) ^ src 



V = 1,C = 0 

v=o,c=o 

V=l,c=l 



Instruction format : 



G format : 

CHK. @:G LEA, LEA 



A format : 

CHK.@:AMEM,SEA 
CHK. @:A SEA, MEM 



Si SO, 0 , o , 1 , 1 . 1 . 1 ,M7 M6 M5M4M3M2 M1,M0 



1 



0 N7 N6.N5 N4N3 N2 N1 NO 



M<7:0> = src, long addressing mode only 

N<7:0> = mem. long addressing mode only 




When DO - 0, mem is memory specified by A<12:0> and src by m<5:0>. 
WhenDD = 1, mem and src are exchanged. 



Flag status change : z SVC 

3 



Operation size : B W D 




Notes 



size = 2 :word 

tTs^ect immediate mode inhibited as mem addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only whenDD - 0. 





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V 

TLCS-9000 INSTRUCTION SET MANUAL 



CHKS mem, src: Check Signed Bound 




Operation : if src (mem) (signed) then if src < (mem + size) then V = 0, C = 0 else 

V = 1, C = 1 else V = l, C = 0 

Description : Checks with sign whether src is equal to or larger than (mem) and less 



than (mem + size). 

src < (mem) V = l, C = 0 

(mem)^ src < (mem + size) V = 0, C = 0 

(mem + size) ^ src V=l, C=1 

Instruction format : 



G format : 
CHKS.0:G 



LEA, LEA 



51 0 . 0 ■ 1 ■ 1 . 1 ■ 1 


M7 


M6 


M5 


M4 
1 1 


M3 


M2 


Ml 


MO 




. N7 


N6 


N5 


t N4 | 


N3 


N2 


N1 


NO 


J 


J 


J 






J 


J 


J 



M<7:0> = src, long addressing mode only 
N<7:0> = mem, long addressing mode only 



A format : 

CHKS.0:A 

CHKS.0:A 



MEM, SEA 
SEA, MEM 



S V°| 1 


,1,1 , m5 , m4 , 1 


DD 
I 1 


0 


I 1 I ° 


m3 


m2 


t ml 


m0 


J^I 


A12 All A10 | A9 ( A8 


, A7 , 


A6 


A5 A4 


A3 


A2 


| A1 


AO 


J L 




J 1 


J 


J 




J 



When DD = 0, mem is memory specified by A<12:0> and src by m<5:0>. 
When DD = 1, mem and src are exchanged. 



Flag status change : z S v c 




Operation size 



B W D 




Notes : size = 2:word 

size = 4 :double word 

Register direct and immediate mode inhibited as mem addressing mode. 
m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 




55 





-ri r~c nnnn inktriITTION SET MANUAL 




Operation : dst +- 0 
Description : Loads 0 in dst. 

Instruction format : 



CLR.0 LEA 

M<7:0> = dst 

Flag status change : 



Notes : Immediate mode inhibited as dst addressing mode. 




Operation size : b W D 

oToTo 




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TLCS-9000 INSTRUCTION SET MANUAL 




CP dst, src : Compare 

Operation : dst -src 

Description : Compares the contents of dst with src and reflects the result in 

condition code flag CC. 

Instruction format : 




S format : 

CP.@:S Reg, SEA 

CP.@:S SEA, Reg When DD = 0, dst isspecified by R<3:0> and src by m<5:0> 

When DD = 1, dst and src are exchanged. 




G format : 

CP.@:G LEA, #8 
CP.@:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



SI. SO 0 



II 1 



1 M7 M6 M5 , M4 . M3 . M2 . Ml MO 




1 



0 . N7 . N6 N5 , N4 N3 N2 N1 NO 




I format: 

CP.@:I LEA, #16 
CP.@:I LEA, #32 



0 SS 0 



0 .M7.M6.M5 M4.M3 M2 Ml MO 




#<15:0> 




1 L — J L 

M<7:0> = dst 



1, 



#<31:16> 
— I 1 1. 



L — i 1 I...J 



A format : 

CP.@:A MEM, SEA 
CP.@:A SEA, MEM 



51 , 50 . 1 


1 1 1 1 1 


DD 


, ° 


, 0 


, ° 


m3 


m2 


ml 


mO 


0 ■ 1 ■ 0 


A12 All A10 ( A9 ( A8 


if! 




ifi 










| AO 



When DD = 0, dst is memory specified by A< 12:0> and src by m<5:0>. 
When DD = 1, dst and src are exchanged. 



I 



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Flag status change : z S v C 



Operation size : b 



W 





Notes 



#<3116> ini format is used when the operation size is double wori 
^m 4 = uTquick immediate) and m5m4 = 00 (register direct, in S format 



allowed only when DD — 0. 

Immediate mode inhibited as dst addressing mode. 
m5m4 = 11 (quick immediate) in A format allowed only 



when DD 






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TLCS-9000 INSTRUCTION SET MANUAL 



CPC dst, src : Compare with Carry Flag 



Operation : dst -src -C 

Description : Subtracts the contents of src and carry flag C from the contents of dst, 

then reflects the result in condition code flag CC. 

Instruction format : 



G format : 

CPC.@:G LEA, #8 
CPC. @:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



s V°. 0 .°i ii i 1 . 1 


■ 1 . M7 I 


M6 


M5 


M4 


M3 


M2 


Ml 

| 


t M0 


O 

_ 

o 

o 


0 


, N7 


N6 


N5 


N4 


N3 


N2 


N1 


t NO 


J 


J L 




J 


J 


J 


J 


J 





A format : 

CPC. A MEM, SEA 
CPC. @:A SEA, MEM 

When DD = 0, dst is memory specified by A<12:0> and src by m<5:0>. 
When DD = 1, dst and src are exchanged. 



si } SO [ 1 t 1 t 1 | m5 | m4 t 1 | DD | 0 | 0 | 0 | m3 t m2 f ml ( mO 
1,1,0 | A12A11A10 | A9 f A8 ( A7 ^ A6 | A5 [ A4 | A3 | A2 [ At [ AO 



Flag status change : z S V C 




Operation size 



: B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

The Z flag is set to 1 when the Z flag = 1 and the operation result = 0; 
otherwise, cleared to zero. 



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TLCS-9000 INSTRUCTION SET MANUAL 



CPL 



dst : One's-Complement 



Operation : dst *— one’s-complement of dst 

Description : Loads one’s-complement of dst (0/1 inverted values of bits) in dst. 
Instruction format : 



CPL.0 LEA 



SI SQ | 1 < Q t 1 | 0 | 0 | 0 | M7 | M6 | M5 ) M4 | M3 | M2 | M1 | MO 



M<7:0> = dst 



Flag status change : z S V C Operation size : b W D 




Notes : Immediate mode inhibited as dst addressing mode. 







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TLCS-9000 INSTRUCTION SET MANUAL 

CPSN dst, src, cnts : Compare String (Unmatch detection) 

Operation : dst - src, cnts *— cnts - 1 , Repeat until dst =£ src or cnts = 0 

Description : Compares the contents of dst with src, then decrements the contents o 

cnts by 1. Unless dst * src or cnts = 0, repeats the operation. 

Instruction format : 




CPSN. (a 
CPSN.0 



LEA, #8 , Reg 
LEA, LEA, Reg 



SI ( so 


1° 


, 0 I 11 I 1 I 1 , 1 


, M7 | 


M6 


MS. 


M4 


M3 


M2 


Ml 


MO 


1 , R3 


, R2 


R1 R0 0 0 4 


N7 


N6 


| N5 [ 


N4 


N3 


N2 


N1 


NO 


1 


J 


J 1 1 1 1 


J L 








J 


J 


J 


J 



M<7:0> 

N<7:0> 

R<3:0> 



src When II = 0, immediate data (8 bits, signed) 
When II = 1, long addressing mode 
dst, long addressing mode only 
cnts 



Flag status change : z S V C 




Operation size 



B W D 




Notes : cnts always consists of words. 

Flags are set according to the comparison result (dst-src). 

Effective addresses of src and dst are recalculated at every repetition. 



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TLCS-9000 INSTRUCTION SET MANUAL 



CPSZ dst, src. cnts : Compare String (Match detection) 




Operation : dst -src, cnts ■♦—cnts- 1, Repeat until dst — src or cnts — 0 

Description : Compares the contents of dst with src, then decrements the contents of 

cnts by 1. Unless dst = src, or cnts = 0, repeats the operation. 

Instruction format : 



CPSZ.0 LEA, #8, Reg 
CPSZ. (3 LEA, LEA, Reg 



S1 S0| 


0 


, ° 


, " I 1 I 1 


1M7 


M6 
J 


M5 
J 


M4 
J 


M3 


1 M2 


Ml 
J 


1 MO 


rr 


R3 


R2 


R1 


R0 0 0 


, o 


N7 


N6 


N5 
J 


N4 




N2 
J 


N1 
J 


NO 

J 


1 1 


L 


J 


J 1 1 


J 


J 


J 


J 



M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 
R<3:0> = cnts 



Flag status change : z S V C 




Operation size 



B W D 




Notes : cnts always consists of words. 

Flags are set according to the comparison result (dst-src). 

Effective addresses of src and dst are recalculated at every repetition. 




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V 



TLCS-9000 INSTRUCTION SET MANUAL 



CSF : Complement of Sign Flag 

Operation : S «— Inverted value of S 
Description : Inverts the contents of sign flag S. 
Instruction format : 




CSF 




Flag status change 




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TLCS-9000 INSTRUCTION SET MANUAL 



CVF : 



Complement of Overflow Flag 




Operation : V <- inverted value of V 
Description : Inverts the contents of overflow flag V . 

Instruction format : 



CVF 




Flag status change : z S V C 

I - I _ I . I - 




TOSHIBA 



l 



CZF: Complement of Zero Flag 



TLCS-9000 INSTRUCTION SET MANUAL 



vy 



Operation : Z «— inverted value of Z 
Description : Inverts the contents of zero flag Z 
Instruction format : 



CZF 




Flag status change : z S V C 



* 



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TLCS-9000 INSTRUCTION SET MANUAL 




Dl : Disable Interrupt 




Operation : El 0 

Description : Resets interrupt enable flag El of the status register PSW to 0. Then 

only non-maskable interrupts can be accepted. 

Instruction format : 



DI 

Flag status change : z S V C 










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TLCS-9000 INSTRUCTION SET MANUAL 



D1V dst, src : Unsigned Divide 




Operation : dst *— dst + src (unsigned) 

Description : Unsigned-divides the contents of dst by the contents of src, then loads 

the quotient in the lower half of dst and the remainder in the upper half 
of dst. 

Instruction format : 



G format : 

DIV.@:G LEA, #8 
DIV.@:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



SI SO 0 0 II 1 


1 


1 M7 


M6 


M5 M4 M3 


M2 


Ml 


M0 


1 1 1 1 1 


1 


1 1 


1 


1 1 1 


1 


I 


1 


1.01.0.1 1 


1 


0 N7 


N6 


N5 N4 N3 


N2 


N1 


NO 


1 1 1 1 1 


J 


J 1 


J 


J 1 1 


J 


J 


J 



A format : 

DI V . @ : A MEM , SEA 
DIV.@:A SEA, MEM 



51 , 50 . 1 . 1 . 1 . m5 , m4 i 


1 ( D D| 


° I 1 


1 ° I m3 


I m2 


I m1 


| m0 


1 1 0 A12 All A10 A9 


A8 A7 


A6 A5 


A4 A3 


A2 


A1 


{ A0 


1 1 1 1 


1 L 


1 


J 1 


J 


J 





When DD = 0, dst is memory specified by A<12:0> and src by m<5:0>. 
When DD = 1, dst and src are exchanged. 



Flag status change : z S V c 




Operation size 



B W D 




Notes : Data size: 

8 bit «- 16 bit + 8 bit, remainder 8 bit : byte operation 

16bit+- 32 bit +16 bit, remainder 16 bit : word operation 

dst is read and writen in double size of the operation size. 

Immediate mode inhibited as dst addressing mode. 

m5m4 = ll(quick immediate) in A format allowed only when DD = 0. 

The V flag is set to 1 when the division result is an overflow (devided by 0 or 
cannot be expressed in the dst size), and the contents of dst are set to 
indeterminate. 

MSB of sign-extended immediate data must be “0”. 4 immediate data needs 
to be sign-extended and its MSB is “1”, sign-extended bits are all Is, and data 
isn’t expressed is BCD. 

G format and II = 0 : Byte operation — 00— FFH 

Word operation — 00— 7FH 



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A format, DD = 0and SEA = Quick Imm : 0~7 

(RWntt), (— RWn), (RDn + + ), and (— RDn) in addressing mode art 
incremented or decremented by the operation size. 



TLCS-9000 INSTRUCTION SET MANUAL 




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TLCS-9000 INSTRUCTION SET MANUAL 



DIVS dst, src : Signed Divide 




Operation : dst «- dst src (signed) ' 

Description : Signed-divides the contents of dst by the contents of src, then loads the 

quotient in the lower half of dst and the remainder in the upper half of 
dst. 

Instruction format : 



G format : 

DIVS.@:G 

DIVS.@:G 



LEA, #8 
LEA, LEA 



si , SO ( 0 ( 0 t II ( 1 t 1 ( 1 ( M7 ( M6 ( M5 ( M4 | M3 : M2 ( 


Ml MO 


1 I ° I 1 I ° I 1 I 1 I ’ 1 1 ,N7,N6 | N5 | N4 | N 3| N2 | 


N1 ( NO 



M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



A format : 

DIVS.@:A MEM, SEA 
DIVS.@:A SEA, MEM 

When DD = 0, dst is memory specified by A< 12:0> and src by m<5:0>. 
When DD = 1, dst and src are exchanged. 



51 , S °, 1 . 1 . 1 1 


. DD | 


0 


I 1 I ° 


r 3 


m2 

| 


ml 

| 


t mO 


1,1,1 A12 All ,A10, A9 , A8 


A7 


A6 


A5 A4 


A3 


A2 


A1 


AO 


J L 




J 1 


J 


J 


J 





Flag status change : z S V C 




Operation size 



B W D 




Notes : Data size: 

8 bit «— 16 bit 8bit> remainder 8 bit : byte operation 

16bit'«- 32 bit 16 bit, remainder 16 bit : word operation 
dst is read and writen in double size of the operation size. 

Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

The V flag is set to 1 when the division result is an overflow (devided by 0 or 
cannot be expressed in the dst size), and the contents of dst are set to 
indeterminate. 

(RWn++), (— RWn), (RDn++), and (— RDn) in addressing mode are in 
cremented or decremented by the operation size. 



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DJNZ dst. disp : Decrement and Jump Non-zero 




Operation : dst *— dst — 1, if dst =£ 0 then PC *- PC + disp 

Description : Decrements the contents of dst by 1. If the result is other than 0, the 

program restarts from PC + disp. 

Instruction format : 



DJNZ LEA, disp 



1 1 , ss . 1 . 1 . 


0 ( 1 ( 1 | 1 ) M7 | M6 | M5 | 


M4 ( M3 | 


M2 ( M1 ^0 


1 t 1 ( 1 | D12D11D10 1 D9 ( D8 | D7 | D6 | D5 | 




02^^ 0 



M<7:0> = dsto 

disp = D<12:0>, but since always = 0, D<0> is not included in the 
instruction code. 



Flag status change : 


Z 


s 


V 


C Operation size : 


B 


w 


D 

1 ■ 1 






- 


- 


FI 


— 


O 


0 



Notes : Immediate mode inhibited as dst addressing mode. 

disp (D < 12 : 0 > ) is handled as signed. 



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TLCS-9000 INSTRUCTION SET MANUAL 



DJNZC dst, cond, disp : Decrement. Conditional and Jump Non-zero 



Operation 

Description 



dst <— dst— 1, if CC is false and dst^ 0 then PC *- PC + disp 




Decrements the contents of dst by 1. If the operand condition is false 
and the decrement result is other than zero, the program restarts 
execution from PC + disp. Otherwise, the program moves to the next 
instruction. 



Instruction format : 
DJNZC LEA, cond , disp 



1 j SS t 1 | 1 | 0 t 1 | 1 | 1 [ M7 | M6 | M5 | M4 | M3 | M2 [ M1 | MO 

C3 C2 Cl D12 Dll DIO D9 D8 D7 D6 D5 D4 D3 D2 D1 CO 
I I I I I I I I I I I I I I I 

M<7:0> = dst 0 

disp = D< 12:0>, but since always D<0> = 0, D<0> is not included in 
the instruction code. 



C3 C2 Cl 
0000 : 
0001 : 

0010 : 
0011 : 
0100 : 
0101 : 
0110 : 
0111 : 
1000 : 
1001 : 
1010 : 
1011 : 
1100 : 
1101 : 
1111 : 
Flag 



CO : Loop exit conditions can be written as follows: 

DJNZC LEA,C,displ3 C=1 (Carry set ) Notation C can also be written as ULT (Lower) 

C=0 (Carry Clear ) Notation NC can be also written as UGE 



DJNZC LEA,NC,displ3 



Z 

Z 

V 



1 

0 

>1 



s=o 



DJNZC LEA,Z,displ3 
DJNZC LEA,NZ,displ3 
DJNZC LEA,OV,displ3 
DJNZC LEA,N0V,displ3 V=0 
DJNZC LEA,MI,displ3 S-l 
DJNZC LEA,PL,displ3 
DJNZC LEA,LE,displ3 
DJNZC LEA,GT,displ3 
DJNZC LEA,LT,displ3 
DJNZC LEA,GE,displ3 
DJNZC LEA,ULE,displ3 C+Z=l 
DJNZC LEA,UGT,displ3 C+Z=0 



(High or Same) 
(EQual ) 

(Not Equal) 
(overflow Set) 
(overflow Clear) 
(Minus) 

(PLus) 

Z+S*V=1 (Less or Equal) 
Z+S‘V=0 (Greater Than) 
S*V=1 (Less Than) 

S'V=0 (Greater or Equal) 

(Low or Same) 
(Higher) 



DJNZC LEA.A.displ3 (Always) 

status change : z S V C Operation size 



B W 




Notes : The loop exit condition A (Always) is insignificant, because the program 

unconditionally moves to the next instruction. 

Immediate mode inhibited as dst addressing mode, 
disp (D< 12 : 0>) is handled as signed. 



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TLCS-9000 INSTRUCTION SET MANUAL 



El : Enable Interrupt 



Operation : El ■*— 1 

Description : Sets interrupt enable flag El of status register PSW to 1. The interrupt 

level is set to the level specified by IM < 3:0 > . 

Instruction format : 

El 

Flag status change : z S V C 




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TLCS-9000 INSTRUCTION SET MANUAL 



EX dst1,dst2 : Exchange 

Operation : dstl * — * dst2 

Description : Exchanges the contents of dstl and dst2. 
Instruction format : 




S format 



EX . @ : S Regl ,Reg2 



G format : 

EX.@:G LEA, LEA 



A format : 

EX.@: A MEM, SEA 
EX.@:A SEA, MEM 



51 1 50 , 


1 


, 1 , 1 


1 

1 1 


1 

| 


0 


, T3 


T2 

| 


| T1 


| T ° 


| R3 


| R2 


R1 

| 


R0 

1 


T<3:0> 


- 


dstl 
























R<3:0> 


■ 


dst2 
























51 i 50 i 


0 


i 0 i 1 


. 1 , 


1 , 


1 


M7 


M6 


M5 


M4 


M3 


M2 


Ml 


MO 


1 i° i 


0 


■ 0 ■ 1 


1 

J L 


1 

_L 


1 






; N5 


N4 

| 






N1 

| 


{ NO 


M<7:0> 


m 


dst2, long addressing mode only 














N<7:0> 


= 


dstl, long addressing mode only 














S1 .| S0 , 


1 


. 1 . 1 


I m5 ± 


m4 


1 


|DD 


, 0 


0 

1 


, 0 


I m3 


r 2 


i m1 


m0 


rr 


1 


1 


A12 All A10 


A9 


A8 


A7 


A6 


A5 


A4 


A3 


A2 


A1 


1 AO 


1 . J 


L 




J 1 


J L 


L 


J 


J 


J 


J 


J 


J 


J 





When DD = 0, dstl is memory specified by A<12:0> 

and dst2 by m<5:0>. 

When DD = 1, dstl and dst2 are exchanged. 



Flag status change : z S V C 




Operation size 



B W D 




Notes 



Immediate mode inhibited as dstl or dst2 addressing mode. 

Operation sequence which dst is CBP is different depending on the operation 
size and the location of CBP. 

In Byte or Word operation : 

• dstl = CBP, dst2 = Reg — (D Write Reg. 




Write CBP 



• dstl = Reg, dst2 = CBP 



Exchange Bank 
- (D Write CBP 
® Exchang Bank 

® Write Reg. which is the exchanged 
Reg. 



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TLCS-9000 INSTRUCTION SET MANUAL 




In Double word operation : 

• dstl = CBP, dst2 = Reg - (D Write lower word Reg. 

<2) Write CBP 
® Exchange Bank 

(J) Write upper word Reg which is the 
exchanged Reg. 

• dstl = Reg, dst2 = CBP -(D Write CBP 

(2) Exchange Bank 

® Write Reg which is the exchanged 
Reg. 



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TLCS-9000 INSTRUCTION SET MANUAL 



EXTS dst : Sign Extend 

\ 

Operation : All bits of dst < upper >■*— signed bits of dst < lower > 
Description : Loads the sign bit of dst lower half to all bits of dst upper half. 
Instruction format : 



EXTS . @ LEA 



1 SS 1 1 0 0 1 1 M7 M6 M5 M4 M3 M2 Ml MO 

I I I I I ! I I I 1 1 1 1 1 1 

M<7:0> = dst 0 



Flag status change : z S V C 




Operation size 



B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

dst is read in the operation size, sign-extended using the lower half of dst, 
then rewritten in the operation size. 



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EXTZ dst : Zero Extend 



Operation : All bits of dst Cupper >«- 0 

Description : Clears the upper half of dst. 

Instruction format : 




EXTZ.0 LEA 




Flag status change : z S V C 



Operation size : b W D 




Notes : Immediate mode inhibited as dst addressing mode. 

dst is read in the operation size, zero-extended for the upper half, the 

rewritten in the operation size. 





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TLCS-9000 INSTRUCTION SET MANUAL 



HALT : Halt CPU 

Operation : Halt CPU 

Description : Halts instruction execution. Receiving an interrupt restarts 

instruction execution. 

Instruction format : 

HALT 

Flag status change : z s v c 






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JP dst : Jump 



Operation : PC *- effective address of dst 

Description : Jumps to the effective address of dst. 

Instruction format : 



JP . (3 LEA 

M<7:0> = dst 

Flag status change : z S V C Operation size 



Notes : Register direct or immediate mode inhibited as dst addressing mode 

The operation size is employed to increment or decrement an address by 
(RWn+ +), (-RWn), (RDn+ +) or (~RDn) in addressing mode. 

When the effective address of dst is odd numbered, jumps to the even 
numbered address obtained by rounding off the least significant bit to . 



B W D 






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TLCS-9000 INSTRUCTION SET MANUAL 




JR disp: Relative Jump 



Operation : PC'*— PC + disp 

Description : Restarts program execution from PC + disp. 
Instruction format : 



JR disp 




disp = D<12:0>, but since always D<0> =0, D<0> is not included in 
the instruction code. 



Flag status change : z S V C 




Notes : disp (D< 12 : 0>) is handled as signed. 





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TLCS-9000 INSTRUCTION SET MANUAL 



JRBC num.abs, disp : Bit Test Relative Jump If Clear 




Operation : ifabs<num>=0 then PC «- PC + disp 

Description : If bit num at absolute address abs is cleared to zero, program execution 

restarts from PC + disp. 

Instruction format : 



JRBC 



num, MEM, disp 



0 


0 

1 


i 0 


, 1 , 1 . 1 . 1 


D8 
1 ! 


i D7 




D5 
1 




i D3 


D2 
1 




0 

1 


B2 


B1 

1 


BO 

1 


A12 All A10, A9 
J 1 1 1 


A8 

1 


A7 

1 


A6 

1 


i A5 


A4 
1 1 


A3 

1 


A2 

1 


L^l 


t AO 



disp = D<8:0>, but since always D<0> =0, D<0> is not included in 

the instruction code. 

abs is memory specified by A< 12:0>. 

num is bit number specified by B<2:0>. 



Flag status change : z S V C 




Operation size 



: B W D 




Notes : disp (D < 8 : 0 > ) is handled as signed. 








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TLCS-9000 INSTRUCTION SET MANUAL 




JRBS num, abs, disp : Bit Test Relative Jump If Set 




Operation : if abs < num > =1 then PC «-PC + disp 

Description : If bit num at absolute address abs is set to one, program execution 

restarts from PC + disp. 

Instruction format : 



JRBS 



num, MEM, disp 


0 


±L 


±1. 


i 1 i ’ . 1 . 1 , D8 


| D? 


06 


| D5 


| D4 


i D3 


i D2 


| D1 , 1 




B2 


B1 

J 




A12 All A10 | A9 ( A8 


[ A7 | 




i A5 


A4 
J 


■« 


A2 

J 


i A1 i A ° 



disp = D<8:0>,butsincealwaysD<0> = 0,D<0> is not included in 

the instruction code. 

abs is memory specified by A<12:0>. 

num is bit number specified by B<2:0>. 



Flag status change •' z S V C 




Operation size 



• B W D 




Notes : disp (D < 8 : 0 > ) is handled as signed. 




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JRC cond.disp : Relative Jump Conditional 



Operation : If CC is true, then PC «— PC + disp 

Description : If the operand condition is true, program execution restarts from 

PC + disp. 

Instruction format : 



JRC cond,disp 

disp = D<8:0>, but since always D<0> =0, D<0> is not included in 
the instruction code. 




C3 C2 Cl 
0000 : 

0001 : 

0010 : 
0011 : 
0100 : 
0101 : 
0110 : 
0111 : 
1000 : 
1001 : 
1010 : 
1011 : 
1100 : 
1101 : 



CO: Jump conditions can 
JRC C,disp9 C=1 

JRC NC,disp9 C=0 

JRC Z,disp9 Z=1 
JRC NZ,disp9 Z=0 
JRC 0V,disp9 V=1 
JRC N0V,disp9 V=0 
JRC MI ,disp9 S=1 
JRC PL,disp9 S=0 
JRC LE,disp9 Z+S* 
JRC GT,disp9 Z+S* 
JRC LT,disp9 S‘V= 
JRC GE,disp9 S'V= 
JRC ULE,disp9 C+Z= 
JRC UGT,disp9 C+Z= 



be written as follows: 

(Carry set) Notation C can also be written as ULT 
(Lower) 

(Carry Clear) Notation NC can also be written as UGE 
(High or Same) 

(EQual) 

(Not Equal) 

(overflow Set) 

(overflow Clear) 

(Minus) 

(PLus) 

V=1 (Less or Equal) 

V=0 (Greater Than) 

1 (Less Than) 

0 (Greater or Equal) 

1 (Low or Same) 

0 (Higher) 



Flag status change : z S V C 




Notes : disp (D <8 : 0>) is handled as signed. 



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LD dst, src : Load 



Operation : dst *— src 

Description : Loads the contents of src in dst. 

Instruction format : 



S format 



LD. @ i S . Reg , SEA 
LD.@:S SEA, Reg 




When DD = 0, dst is specified by R<3:0> ; src, by m<5:0>. 
When DD = 1, dst and src are exchanged. 



G format 



LD . @ : G LEA, #8 
LD.0:G LEA, LEA 



51 . so - 0 . 0 ■ 11 . 1 


, 1 ■ 1 l M7 . 


M6 


M5 


M4 

1 


M3 


M2 


Ml 


MO 


1 0 0 0,0,1 


1 1 N7 


N6 


N5 


N4 


, N3 


, N2 


N1 


NO 


___l 1 1 1 1 


J 1 1 L 




J 


1 


J 


J 


J 


1 



M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



I format 

LD.@:I 

LD.0:I 



LEA, #16 
LEA, #3 2 



0 0 0 0 SS 0 1 1 M7 M6 M5 M4 M3 M2 Ml MO 

I I I I I I I I I I I 1 1 1 1 

#<15:0> 

-i 1 u 

#<31 : 16> 

J I i I. 



I I L J I L J I 1 I L — I 1 L — J — -• 

M<7:0> = dst 



A format 



LD.0:A MEM, SEA 
LD . 0 : A SEA, MEM 



SI SO 1 1 1 m5 m4 1 DD 0 0 0 m3 m2 ml mO 

0 [ 1 | 1 A12A11A10 | A9 | A8 | A7 | A6 | A5 : A4 t A3 | A2 | A1 | AO 

When DD = 0, dst is memory specified by A<12:0> ; src, by m<5:0>. 
When DD = 1, dst and src are exchanged. 



Flag status change : z S V C Operation size : b W D 







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Notes : # <31:16 > in I format is used when the operation Size is double word. 

m5m4 = 11 (quick immediate) and m5m4 = 00 (register direct) in S format 
allowed only when DD = 0. 

Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 



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LDA dst, src : Load Effective Address 




Operation : dst <— effective address of src 
Description : Loads the effective address of src in dst. 
Instruction format : 



A/ rV\ 

LDA . @ LEA , LEA 



1 SS 1 1 


0 0 0 0 M7 


M6 


M5 


M4 


M3 


M2 


Ml 


MO 


1 1 1 


1 1 I 1 I 


I 


I 


1 1 




1 


1 


1_ 


10 0 1 


01 1 1 N7 


N6 


N5 


N4 


N3 


, N2 


, N1 


NO 





J 1 1 1 1 


J 


J 


J L 




j 


j 


J 



M<7:0> = src, long addressing mode only 
N<7:0> = dst, long addressing mode only 



Flag status change : z S V C 




Operation size : b W D 




Notes : Register direct or immediate mode inhibited as src addressing mode. 



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LDCF src, num : Load Bit to Carry Flag 

Operation : C *- src < num > 

Description : Loads the contents of bit num in src in carry flag C. 
Instruction format : 




G format : 

LDCF.@:G LEA, #8 
LDCF.@:G LEA, LEA 

M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = src, long addressing mode only 



SI SO 0 0 II 1 

1 1 1 1 1 1 


1 1 M7 M6 

1 1 1 1 


M5 


M4 M3 


M2 Ml 


M0 


110 0 11 
1 1 1 1 1 l 


1 1 N7 N6 

1 1 1 l 




N4 N3 

1 l 


N2 | N1 | 


NO 



A format : 

LDCF.0:A MEM, SEA 
LDCF. A SEA, MEM 

When DD = 0, src is specified by A<12:0> and num by m<5:0>. 
When DD = 1, num and src are exchanged. 



SI SO 1 , 1 1 m5 m4 1 DD 1 0 0 m3 m2 ml 

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 


m0 


1 ( 1 ! 1 A12 All A10 i A9 | A8 | A7 ) A6 | A5 i A4 | A3 ( A2 ( A1 ( 


A0 



Flag status change : z S V C 




Operation size 



B W D 




Notes : m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 




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LDS dst, src, cnts : Load String 




Operation : dst *- src, cnts <— cnts — 1 , Repeat until cnts = 0 

Description : Loads the contents of src in dst, then decrements the contents of cnts by 

1. If the decrement result is other than 0, the operation is repeated. 

Instruction format : 



LDS.0 LEA, #8, Reg 
LDS.@ LEA, LEA, Reg 



M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 
R<3:0> = cnts 



SI so 


, ° 


, ° 


, " ■ 1 . 1 


1 M7 


M6 


M5 


| M4 | 


M3 


M2 


Ml 


MO 


1 R3 


R2 


R1 


73 

O 

o 


1 


N7 


N6 


N5 


N4 


N3 


N2 


N1 


NO 


1 


J 


J 


J 1 1 


J 


J 


J 


J 


J L 




J 


J 


J 



Flag status change : z S V C 




Operation size : b W D 




Notes : cnts always consists of words. 

Effective addresses of src and dst are recalculated at every repetition. 
Immediate and special register (Imm, SP, ISP, PBP, CBP, PSW, IMC, CC) 
mode inhibited as dst addressing mode. 



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LINK disp : Link Stack Frame 

Operation : (-SP)«-R2, R2«-SP, SP*-SP + disp 

Description : Saves the contents of R2 in the stack area, then loads the contents ol 

stack pointer SP in R2, adds the contents of the stack pointer and signed 
disp, and loads the result in the stack pointer. 

Instruction format : 



LINK disp 



1 , 1 , 0 , 0 , 0 [ 0 | 0 [ D8 | D7 | D6 | D5 t D4 f D3 [ D2 f D1 | 1 



Flag status change : z S V C 



Notes : From the point of view of execution speed, it is recommended that the stack 

pointer be an even number. Therefore, the least significant bit of D < 8:0 > is 
always 0. 




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TLCS-9000 INSTRUCTION SET MANUAL 



MAC dst, srcl, src2 : Unsigned Multiply-and-Add Calculation 

Operation : dst ■*— srcl X src2 + dst 

Description : Unsigned-multiplies the contents of srcl by the contents of src2, adds 

the contents of dst to the result, and loads the result in dst. 

Instruction format : 



MAC. @ Reg, LEA, #8 
MAC.0 Reg, LEA, LEA 



M<7:0> = src2 When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = srcl, long addressing mode only 
R<3:0> = dst 



SI 


so 


0 


0 


II 1 


1 1 


M7 


M6 


M5 


M4 


M3 


M2 


Ml 


MO 


1 


1 


| 


1 1 _L 


1 


1 


1 


1 








J 


J 


J 


0 


R3 


R2 


R1 


R0 0 , 


1 0 


, N7 


, N6 


, N5 


N4 


N3 


N2 




( NO 




J 


J 


J 


J 1 L 


1 


j 


J 


j 


1 


1 




J 



Flag status change : z S V C 




Operation size 



B W D 




Notes : Data size : 

16bit «— 16bit+8bitX8bit : byte operation 
32bit<-32bit+16bitXl6bit : word operation 
dst is read and writen in double size of the operation size. 

The flag status changes according to the operation result: (srcl X src2) + dst. 
Immediate mode inhibited as srcl addressing mode. 

MSB of sign-extended immediate data must be “0” . If immediate data needs 
to be sign-externded and its MSB is "1” , sign-extended bits are all Is, and 
data isn’t expressed in BCD 

11 = 0: Byte operation — 00~FFH 
Word operation — 00~7FH 



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Operation : dst «— srcl X src2 4- dst 

Description : Signed-multiplies the contents of srcl by the contents of src2, adds the 

contents of dst to the result, and loads the result in dst. 



Instruction format : 



MACS.0 Reg, LEA, #8 
MACS . @ Reg, LEA, LEA 

When II = 1, long addressing mode 
N<7:0> = srcl, long addressing mode only 
R<3:0> = dst 



Flag status change : z S V C Operation size : b W D 



Notes : Data size : 

16bit «— 16bit+8bitX8bit : byte operation 
32bit *- 32bit+ 16bitX 16bit : word operation 
dst is read and writen in double size of the operation size. 

The flag status changes according to the operation result: (srcl X src2) + dst. 
Immediate mode inhibited as srcl addressing mode. 










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TLCS-9000 INSTRUCTION SET MANUAL 



MAX dst, src : Unsigned Maximum Value 

Nj 



Operation : if dst S src (unsigned) then dst *— dst else dst «— src 

Description : Unsigned-compares the contents of dst with the contents of src. If the 

contents of dst are equal to or larger than those of src, they are loaded in 
dst; if smaller, the contents of src are loaded in dst. 

Instruction format : 



G format : 

MAX.@:G LEA, #8 
MAX.@:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



SI SO 0 0 II 1 


1 


1 M7 M6 M5 M4 


M3 


M2 


Ml 


M0 


1 1 1 1 1 


1 


1 1 1 1 1 


1 


1 


1 


1 


1 , 0 0,11,1 


1 


0 N7 N6 N5 N4 


N3 


. N2 


, N1 


NO 





J 


J 1 1 1 


J 


j 




J 



A format : 

MAX. A MEM, SEA 
MAX. @:A SEA, MEM 



51 l S0 , 1 , 1 . 1 mSmA, 1 


| DD . 


0 


,° 


1 1 I" 3 


m2 

1 


, m1 


j mO 


1 1 0 A12 All A10 A9 A8 


, A7 , 


A6 


, A5 


,A4 A3 


A2 


A1 


A0 


1 1 1 1 1 1 1 


J L 





J 


J 1 


J 


J 


1 



When DD = 0, dst is memory specified by A<12:0>; src, by m<5:0>. 
When DD = 1, dst and src are exchanged. 



Flag status change : z S V C 




Operation size : b W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

The flag changes according to the dst-src result. 

MSB of sign-extended immediate data must be “0”. If immediate data needs 
to be sign-extended and its MSB is “1”, sign-extended bits are all Is, and data 
isn’t expressed is BCD. 

G format and II = 0 : Byte operation — 00~FFH 

Word operation — 00~7FH 

A format, DD = 0 and SEA = Quick Imm : 0~7 



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MAXS dst. src : Signed Maximum Value 




Operation : if dst S src (signed) then dst <- dst else dst +- src 

Description : Signed-compares the contents of dst with the contents of src. If the 

contents of dst are equal to or larger than those of src, they are loaded in 
dst; if smaller, the contents of src are loaded in dst. 

Instruction format : 



G format : 

MAXS.@:G LEA, #8 
MAXS.@:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



SI | s° | 


0 , 0 , " , 1 , 


1 1 M7 

1 1 1 J 


M6 


M5 

1 1 


M4 

1 1 


M3 


M2 
1 


Ml 
1 


MO 




0 , 1 ■ 1 , 1 




N6 

1 


lL 


N4 

1 1 


l!L 


N2 

1 


N1 

1 


i NO 



A format : 

MAXS.@:A 

MAXS.@:A 



MEM, SEA 
SEA, MEM 



SI [ SO [ 1 t 1 , 1 ,m5 | m4 | 1 , PD , 0 , 0 , 1 , m3 , m2 , ml , mO 
1 A12 All A10 A9.A8 A7 ,A6 A5,A4 A3 A2A1 AO 



When DD = 0,dst is memory specified by A<12:0> and src by m<5:0>. 
When DD = 1, dst and src are exchanged. 



Flag status change : z S V C 




Operation size : b W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 
The flag changes according to the dst-src result. 









TOSHIBA TLCS-9000 INSTRUCTION SET MANUAL 



MIN dst, src : Unsigned Minimum Value \ 



Operation : if dst ^ src (unsigned) then dst *— dst else dst *- src 

Description : Unsigned-compares the contents of dst with the contents of src. If the 

contents of dst are equal to or smaller than those of src, they are loaded 
in dst; if larger, the contents of src are loaded in dst. 

Instruction format : 



G format : 

MIN.@:G LEA, #8 
MIN.@:G LEA, LEA 



A format : 

MIN.@:AMEM,SEA 
MIN. 0:A SEA, MEM 



S, ,S0, 1 , 1 , 1 ,mS,m4, 1 ,DD, 0,0,1 ,m3, 


m2 ml mO 


1 ( 0 t 0 A12A11 A10 | A9 | A8 | A7 ) A6 | A5 | A4 | A3 | 


A2 ( A1 | A0 



When DD = 0, dst is memory specified by A<12:0>; src, by m<5:0>. 
When DD = 1 , dst and src are exchanged. 



SI ( SO ( 0 f 0 ( II ( 1 t 1 ! 1 | M7 | M6 | M5 | M4 | 


M3 M2 Ml 


M0 


1 . 0 , 0 . 1 , 1 , 1 - 0 , 0 ,N7 1 N6 i N5 | N4 i 


N3 | N2 ( N1 ( 


NO 



M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



Flag status change : z S V C 




Operation size : b W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

The flag changes according to the dst-src result. 

MSB of sign-extended immediate data must be “0”. If immediate data needs 
to be sign-extended and its MSB is “1”, sign-extended bits are all Is, and data . 
isn’t expressed is BCD. 

G format and II = 0 : Byte operation — OO'-FFH 

Word operation — 00~7FH 

A format, DD = 0 and SEA = Quick Imm : 0~7 



93 






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TLCS-9000 INSTRUCTION SET MANUAL 



MINS dst, src 



Signed Minimum Value 



Operation : if dst ^ src (signed) then dst <— dst else dst *— src 

Description : Signed-compares the contents of dst with the contents of src. If the 

contents of dst are equal to or smaller than those of src, they are loaded 
in dst; if larger, the contents of src are loaded in dst. 

Instruction format : 



G format : 

MINS.@:G LEA, #8 
MINS.@:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



SI ^ so | 0 | 0 | II | 1 , 1 | 1 1 M7 | M6 | M5 | M4 | M3 , M2 [ Ml | MO 
1 | Q | Q | 1 | 1 | 1 , 0 , 1 , N7 | N6 , N5 , N4 | N3 , N2 | N1 , NO 



A format : 

MINS . @ : A 
MINS.@:A 





St ,50, 1 


1 1 m5 m4 

i 1 1 l 1 


1 DD 


1° 


0 

1 


I 1 I" 3 




ml 
J 


t mO 


MEM, SEA 
SEA, MEM 


1 i 0 . 1 


,A12 All ,A10, A9 , 


A8 , A7 


1^1 


A5 
J 




ifi 


A1 

J 


t AO 



When DD = 0, dst is memory specified by A<12:0>; src, by m<5:0>. 
WhenDD = 1 , dst and src are exchanged. 



Flag status change : z S V C 




Operation size 



B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 
The flag changes according to the dst-src result. 



94 





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TLCS-9000 INSTRUCTION SET MANUAL 



MIRR dst : Mirror Exchange 






Operation : dst<MSB:LSB> «-dst<LSB:MSB> 

Description : Mirror-exchanges the contents of dst as the bit pattern image. 
Instruction format : 



MIRR.0 LEA 



SI SO 1 0 0 0 



M<7:0> = dst 



1 M7 M6 M5 M4 M3 M2 Ml MO 



Flag status change : z S V c Operation size : b W D 

- 1 - I - I - I lo lo lo 




Notes : Immediate mode inhibited as dst addressing mode. 



95 






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TLCS-9000 INSTRUCTION SET MANUAL 



MUL dst, src : Unsigned Multiply 



Operation : dst dst X src (unsigned) 

Description : Unsigned-multiplies the contents of dst by those of src, then loads the 

result in dst. 

Instruction format : 



G format : 

MUL.@:G LEA, #8 
MUL . @ : G LEA , LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



o“ 

o" 


1 1 1 1 


1 M7 M6 


M5 M4 M3 M2 Ml M0 


10 10 1 

1 1 1 1 l 




0 N7 N6 

1 1 l 


N5 N4 N3 N2 N1 NO 

1 1 1 1 1 



A format : 

MUL. @:A MEM, SEA 
MUL.@:A SEA, MEM 

When DD = 0, dst is memory specified by A<12:0>; src, by m<5:0>. 
When DD = 1, dst and src are exchanged. 



S1 , S0 , 1 . 1 , 1 1 . DD , 0 . 


1 0 m3 m2 ml mO 

1 1 1 1 1 


1 ( 0 ( 0 A12 All A10 | A9 ( A8 ( A7 ( A6 | 


A5 ( A4 ( A3 ! A2 ( A1 ( A0 



Flag status change : z S V C 




Operation size 



B W D 




Notes : Data size: 

16 bit «- 8 bit X 8bit : byte operation 

32 bit «— 16 bit X 16bit: word operation 

dst is read and writen in double size of the operation size. 

Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

MSB of sign-extended immediate data must be “0”. If immediate data needs 
to be sign-extended and its MSB is “1”, sign-extended bits are all Is, and data 
isn’t expressed is BCD. 

G format and II = 0 :Byte operation — 00~FFH 

Word operation — 00~7FH 

A format, DD = 0 and SEA = Quick Imm : 0~7 
(RWn++), (-RWn), (RDn++), and (-RDn) in addressing mode are 
incremented or decremented by operation size. 



96 








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TLCS-9000 INSTRUCTION SET MANUAL 



MULS dst, src : Signed Mutiply 




Operation : dst ■*— dst X src (signed) 

Description : Signed-multiplies the contents of dst by those of src, then loads the 

result in dst. 

Instruction format : 



G format : 

MULS . @ : G LEA, #8 
MULS.@:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



SI SO 0 0 II 1 


1 


1 M7 


M6 


M5 


M4 


M3 


M2 


Ml 


MO 


1 1 1 1 1 


1 


1 1 


I 


1 


1 


1 




1 


I 


I 


1 0.1 0 1 1 


0 


1 N7 


N6 


N5 


N4 


N3 


N2 


N1 


NO 


1 1 1 1 1 


J 


J 1 


J 


J 


1 


l 




J 


J 


J 



A format : 

MULS.@:A 
MULS . @ : A 



MEM, SEA 
SEA, MEM 

When DD = 0, dst is memory specified by A< 1 2 : 0 > ; src, bym<5:0>. 
When DD = 1, dst and src are exchanged. 



S V°, 1 


i 1 , 1 . m5 . m4 . 1 


, DD | 


0 


I 1 1° 


r 3 


m2 


I m1 


mO 




o . 1 


A12 All A10 A9 A8 


A7 


A6 


A5 A4 


A3 


A2 


. A1 


f AO 


1 i 





J 


J L 




J 


J 


J 


J 





Flag status change : z S V C 




Operation size 



B W D 




Notes : Data size: 

16 bit *- 8 bit X 8bit : byte operation 

32 bit «— 16 bit X 16bit: word operation 

dst is read and writen in double size of the operation size. 

Immediate mode inhibited as dst addressing mode. 
m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 
(RWn++), (— RWn), (RDn++), and (— RDn) in addressing mode are 
incremented or decremented by operation size. 



97 








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TLCS-9000 INSTRUCTION SET MANUAL 



NEG dst : Negate 



Operation : dst ■*— 0 — dst 

Description : Subtracts the contents of dst from 

Instruction format : 



U 

0, then loads the result in dst. 



NEG.0 LEA | SI | SO t 1 | 0 ^ 1 f 0 ( 0 [ 1 | M7 f M6 | M5 | M4 | M3 | M2 | M 1 ( MO 

M<7:0> = dst 



Flag status change : z S V c 




Operation size : b W D 




Notes : Flags are set according to the operation result. 

Immediate mode inhibited as dst addressing mode. 



98 





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TLCS-9000 INSTRUCTION SET MANUAL 



NOP : No Operation 



Operation : No operation 

Description : No operation, moves to the next instruction. 
Instruction format : 




NOP 



0 1 

1 l 


1 1 1 

1 1 — l 


1 1 
1 l 


110 10 
1 1 1 1 l 


0 0 0 0 

1 1 1 



Flag status change : z S V C 




99 





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TLCS-9000 INSTRUCTION SET MANUAL 



OR dst, src : Logical OR 

Operation : dst •*— dst OR src 
Description : ORs the contents of dst and src, then loads the result in dst. 

Instruction format : 




S format : 

OR.0:S Regl,Reg2 



G format : 

OR . @ : G LEA, #8 
OR . 0 : G LEA, LEA 





.iS. 


1 


1 

| 


1 

1 


1 0 


1 

1 


1 0 


, T3 


, T2 


, T1 


i T0 


i R3 


| R2 


R1 

1 


, R0 


T<3:0> 




dst 


























R<3:0> 




src 


























SI 


| S °I 


0 


, 0 


II 

1 


1 

1 


1 

1 


1 

1 


M7 

1 


M6 

1 


M5 

1 


M4 

I 


M3 


M2 

I 


Ml 

I 


MO 


1 


, 1 , 


0 


, o 


, 0 


1 


0 


1 


N7 


N6 


. N5 


N4 


N3 


N2 


N1 


NO 


■ 


J L 


— — — 


J 


J 


J — 


J 


J — 


J 


J 


j 


J 


J 


J 


J 


1 



M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



I format: 

OR. 0:1 LEA, #16 
OR.0:I LEA, #32 



A format : 

OR.0:A MEM, SEA 
OR . 0 : A SEA, MEM 



0 




0 


, 0 


SS 1 
1 1 1 


0 1 M7 M6 

1 1 1 1 


M5 


M4 


M3 M2 


Ml 


^0 












#<15:0> 














1 1 




1 


1 1 1 


. . . 1 




| 


1 1 


| 


1 


1 

1 

1 

• 


1 1 




-L-. 


J | L 


#<31 : 16> 

J | i |. 




1— . 


] J 


L„_ 


1 

1 

i J 


M<7:0> 


= 


dst 
















SI 


I 50 1 


1 


jJ. 


, 1 ! m5 . 


m4 , 1 , DD , 1 . 


0 


i° 


m3 m2 


ml 

1 


mO 

1 


0 


jAl 


1 


A12 All A10 | 


A9 ( A8 | A7 | A6 ( 


A5 


A4 






[ AO 



When DD = 0, dst is memory specified by A<12:0>; src, by m<5:0>. 
When DD = 1, dst and src are exchanged. 



Flag status change : 



Z 


s 


V 


c 


* 


* 


0 


0 



Operation size : b W D 




100 



1 







TOSHIBA 



Notes : 



V 

TLCS-9000 INSTRUCTION SET MANUAL 



# <31:16 > in I format is used when the operation size is double word. 

Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 



101 




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TLCS-9000 INSTRUCTION SET MANUAL 



ORCF src, num : Bit Logical OR with Carry Flag 




Operation : C *- C OR src < num > 

Description : ORs the contents of carry flag C with bit num in src, then loads the 

result in C. 

Instruction format : 



G format : 

ORCF.@:G LEA, #8 
ORCF.@:G LEA, LEA 

M<7:0> = num. When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = src, long addressing mode only 



SI SO 0 0 II 1 1 1 M7 M6 M5 M4 


M3 ( M2 | Ml ^0 


1 1 0 0 1 1 0 1 N7 N6 N5 , N4 

1 1 1 1 1 1 1 1 1 1 1 1 


N3 ( N2 j N1 ( NO 



A format : 

ORCF. A 
ORCF. A 



MEM, SEA 
SEA, MEM 



SI SO 1 


1 1 m5 m4 1 

l 1 1 1 1 


|DD ( 1 


1 ° 


0 

1 


r 3 


( m2 ( ml 


m0 
J 


rr 


0 1 


A12 All A10 A9 A8 


A7 A6 


, A5 


,A4 


, A3 


> 

po 

> 




LLl 


1 


J 1 1 1 1 


J 1 


J 


J 


J 



When DD = 0, src is memory specified byA<12:0> 
and num is number specified by m<5:0>. 

When DD = 1, num and src are exchanged. 



Flag status change: z S V C 




Operation size 



: B W D 




Notes : m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 



102 





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TLCS-9000 INSTRUCTION SET MANUAL 



POP dst : Pop from Stack 



Operation : dst«-(SP + ) 

When byte : dst <- (SP), SP <- SP + 1 

When word : dst ■«- (SP), SP <-SP + 2 

When double word : dst «— (SP), SP «— SP + 4 

Description : Loads the contents at the memory address specified by the stack pointer 

SP in dst, then adds the number of bytes in the operand to the stack 
pointer. 

Instruction format : 



POP.0 LEA 



SI t SO | 1 t 0 ] 0 | 0 | 0 t 0 t M7 | M6 | M5 f M4 | M3 | M2 | Ml ( MO | 
M<7:0> = dst 



Flag status change : z S V C 




Operation size 



B W D 




Notes : The data is read from the stack area after the effective address of dst is 

calculated. 

Immediate mode inhibited as dst addressing mode. 



103 







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TLCS-9000 INSTRUCTION SET MANUAL 



PUSH src : Push to Stack 

Operation : ( — SP) ■*— src 

When byte : SP «— SP — 1, (SP) «— src 

When word : SP *- SP — 2, (SP) *- src 

When double word : SP *— SP — 4, (SP) <— src 

Description : Subtracts the number of bytes in the operand from stack pointer SP, 

then loads the contents of src in the memory address specified by the 
stack pointer. 

Instruction format : 




PUSH.0 LEA 



SI | SO | 1 t 0 t 0 t 0 t 0 | 1 | M7 { M6 | M5 ( M4 | M3 t M2 | Ml | MO | 
M<7:0> = src 



Flag status change : z S V c 




Operation size 



B W D 




Notes : The data is written to the stack area after src is read. 



104 





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TLCS-9000 INSTRUCTION SET MANUAL 



PUSHA dst : Push Effective Address to Stack 

\I 

Operation : ( — SP) +- effective address of dst 

When word : SP «— SP — 2, (SP) *— effective address of dst 

When double word : SP «- SP — 4, (SP) <- effective address of dst 

Description : Pushes the effective address of dst to the stack area. 

Instruction format : 



PUSHA. 0 LEA 1 , ss < 1 | 1 f 0 < 0 [ 0 | 1 | M7 f M6 < M5 ^ M4 | M3 | M2 [ Ml f MO 

M<7:0> = dst 



Flag status change : z S V C 




Operation size 



• B W D 




Notes : The data is written to the stack area after the effective address of dst is 

calculated. 

Register direct or immediate mode inhibited as dst addressing mode. 



105 





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TLCS-9000 INSTRUCTION SET MANUAL 




Operation : C 0 

Description : Resets carry flag C to 0. 

Instruction format : 






TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 

RET : Return 

Operation : PC *- (SP), SP — SP + 4 

Description : Pops the return address from the stack area to program counter PC, 

then starts program execution from the program address of the restored 
PC. 

Instruction format : 

RET 

Flag status change : z S V C 





107 






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TLCS-9000 INSTRUCTION SET MANUAL 



RETD dis 



Return And Delete Parameter Area 



Operation : PC *- (SP), SP •*- SP + 4, SP *- SP + disp 

Description : Pops the return address from the stack area to program counter PC, 

then adds the disp (signed) value to stack pointer SP. 

Instruction format : 



RETD disp 




Flag status change : z S V C 



Notes : From the point of view of execution speed, it is recommended that the stack 

pointer be an even number. Therefore, the least significant bit of D < 8:0 > is 

always 0. 




TOSHIBA 






RET1 : Return from Interrupt 



TLCS-9000 INSTRUCTION SET MANUAL 



V/ 



Operation : Returns special registers and general-purpose registers from the 

memory stack area or bank. 

Description : Returns special registers and general-purpose registers from the 

memory stack area or bank according to the contents of bit RA in PSW. 
Starts program execution from the program address of the restored 
program counter. 

Instruction format : 



RETI 




Flag status change : z S V C 




Notes : If memory stack, only PC and PSW are restored. 

If bank, PC, PBP, CBP, and PSW are restored. 

Flags are set (restored) according to the restored PSW contents. 
It is used for returns from general interrupt processing routines. 



109 





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TLCS-9000 INSTRUCTION SET MANUAL 



RETS : Return from Single Step Interrupt 




Operation : Restores special registers and general-purpose registers from the 

memory stack area or bank. 

Description : Restores special registers and general-purpose registers from the 

memorystack memory area or bank according to the contents of bit RA 
in PSW. Starts program execution from the program address of the 
restored program counter. 



Instruction format : 



RETS 




Flag status change : z S V C 




Notes : If memory stack, only PC and PSW are restored. 

If bank, PC, PBP, CBP, and PSW are restored. 

Flags are set (restored) according to the restored PSW contents. 

Unlike RETI, no interrupt can be accepted until execution of the next 
instruction is completed. Used as a return instruction from a single step 
interrupt. Ensures implementation of a single step interrupt for every 

instruction. 





TOSHIBA 






TLCS-9000 INSTRUCTION SET MANUAL 



RL dst, num 



Rotate Left with Carrv Fla 



V 



Operation : C & dst *— rotate left C & dst, repeats by the number of num 

Description : Rotates left the result of linking the carry flag to the upper bits of dst. 

Repeats this operation by the number of num. The number of the 
rotation in S format is once only. 

Description figure : 

Instruction format : 




S format : 

RL.@:S LEA, 1 




G format : 

RL.@:G LEA, #8 
RL.@:G LEA, LEA 

M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 




A format : 

RL.@:A MEM, SEA 
RL.0:A SEA, MEM 

When DD = 0, dst is memory specified by A< 12:0> 
and num is number specified bym<5:0>. 

When DD = 1, dst and num are exchanged. 




Flag status change : z S V C Operation size : b W D 



Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

When the number of bits to be shifted is 0, dst and the C flag do not change. 
The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 





Ill 









TOSHIBA 



TLCS-9000 INSTRUCTION SET MANUAL 



RLC dst, num : Rotate Left without Carry Flag 




Operation 



C *— dst< MSB > , dst *— rotate left dst, 

dst < LSB > *— dst < MSB > , repeats by the number of num 



Description : Loads the contents of MSB of dst in carry flag C, rotates left the 

contents of dst, and loads the MSB of dst in LSB . Repeats this 
operation by the number of num. The number of the rotation in S 
format is once only. 



Description figure : 




Instruction format : 



S format : 
RLC.@: S LEA,1 



G format : 

RLC.@:G LEA, #8 
RLC. (3 :G LEA, LEA 

M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



fir 


S0 , 


1 


, o 


, 1 


, 1 


1 


0 


M7 


M6 


M5 


M4 


M3 


M2 


Ml 


MO 1 


1-1. 


L 




1 


I 


| 


| 


| 


| 


| 






| 


| 


| 


l 1 


M<7:0> 


« 


dst 


























l s V°i 


0 


. 0 


i 11 


. 1 


i 1 


i 1 


M7 


M6 


i M5 i 


M4 


M3 


M2 


Ml 


MO 


i 


0 , 


1 


1 


1 


1 


, i 


, 0 


N7 


N6 


N5 


N4 


N3 


N2 


N1 


NO 


1 L 


L 





J 


J 


J 


j 


J 


J 


J 


J L 




J 


J 


J 


J 



A format : 

RLC . @ : A MEM , SEA 
RLC.@:A SEA, MEM 



When DD = 0, dst is memory specified byA<12:0> 
and num is number specified by m<5:0>. 

When DD = 1, dst and num are exchanged. 



SI SO 1 1 1 m5 m4 1 

1 1 1 1 1 1 1 


DD 
1 1 


0 . 1 . 1 


I m3 


r 2 


i m1 


m0 


1 1 0 A12 All A10 A9 A8 


A7 


A6 A5 A4 


A3 


A2 


A1 


| AO 


1 1 1 1 1 1 1 


J L 


1 1 


J 


J 


J 





Flag status change : z S V c 




Operation size 



• B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

When the number of bits to be shifted is 0, dst and the C flag do not change. 
The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 



112 







TOSHIBA 



V 

TLCS-9000 INSTRUCTION SET MANUAL 



RLM dstl , dst2, num : Rotate Left Multi Bit 



Operation 



Lower num bits in dst2&dstl *— rotate left lower num bits in dst2& 
dstl, repeats by the number of num. 



Description 



Links the contents of lower num bits in dst2 with dstl, then rotates left 
by the num bits. 



Description figure : 



dst2 num num dstl 




Instruction format : 



RLM.0 LEA, Reg, #8 
RLM.0 LEA, Reg, LEA 



M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dstl, long addressing mode only 
R<3:0> = dst2 



SI 


so 

J 


±L 




, 11 , 1 , 1 


I 1 , M? 


M6 


M5 

1 


i M4 i 


M3 


M2 


Ml 


t M0 


0 




il i 




i ro i 1 i° 


, 0 ,N7 


, N6 


, N5 


, N4 


N3 


N2 


N1 


NO 




J 1 


J 


j 


J L 




J 


J 



Flag status change : z S V C 



Operation size 



B W D 




Notes : Immediate mode inhibited as dstl addressing mode. 

dst2 always consists of words. The upper bits not used are cleared to zero. 

The lower 3 bits of num are effective when the operation size is byte; the 
lower 4 bits, when the operation size is word/double word. 

When the number of bits to be shifted is 0, dstl does not change, and dst2 is 
cleared to zero. 

operation result write in dst2 and then in dstl. 



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RR dst, num : Rotate Right with Carry Flag 




Operation 



C & dst *- rotate right C & dst, repeats by the number of num 



Description : Rotates right the result of linking the carry flag to the upper bits of dst. 

Repeats this operation by the number of num. The number of the 
rotation in S format is once only. 



Description figure : 




Instruction format: 



S format : 

RR.0:S LEA, 1 




M<7:0> = dst 



G format : 

RR.0:G LEA, #8 
RR.0:G LEA, LEA 



SI | SO | 0 | 0 | II | 1 | 1 [ 1 ^ M7 | M6 | M5 | M4 | M3 ( M2 | Ml | MO 



1 N7 N6 N5 N4.N3.N2N1, NO 




M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



A format : 

RR . 0 : A MEM, SEA 
RR . 0 : A SEA, MEM 



SI SO 1 



1 m5 rr>4 . 1 DD . 0 . 1 . 1 m3 m2 ml mO 



1 | 0 | 1 A12A11 A10 | A9 t A8 ( A7 | A6 t A5 t A4 | A3 | A2 | A1 | AO 



When DD = 0, dst is memory specified byA<12:0> 
and num is number specified by m<5:0>. 

When DD = 1, dst and num are exchanged. 



Flag status change : 





Operation size 



: B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

When the number of bits to be shifted is 0, dst and the C flag do not change. 
The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 



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TLCS-9000 INSTRUCTION SET MANUAL 



RRC dst, num : Rotate Right without Carry Flag 




Operation 



C «— dst < LSB > , dst ■*— rotate right value of dst, 

dst < MSB > •*— dst<LSB>, repeats by the number of num 



Description : Loads the contents of LSB of dst in carry flag C, rotates right the 

contents of dst, and loads the LSB of dst in MSB. Repeats this operation 
by the number of num. The number of the rotation in S format is once 
only. 



Description figure : 




Instruction format : 



S format : 

RRC.@:S LEA,1 



G format : 

RRC.0:G LEA, #8 
RRC. @:G LEA, LEA 



ITT 


SO 


1 


0 


1 


1 


1 


1 


M7 


M6 


M5 


M4 


M3 


M2 


Ml 


MO 1 


1 1 


L 


I 


1 


1 


1 


1 


| 


| 


| 


| 


I 


| 


I 


1 1 


M<7:0> 


= dst 


























K*. 


° 0 


I " 


, 1 


1 1 


1 1 


M7 


M6 


M5 


M4 


M3 


M2 


Ml 


jMO 




0 


1 


1 


1 


1 


1 


1 


N7 


N6 


N5 


N4 


N3 


N2 


N1 


| NO 


1 i 


L 


1 


J 


J 


J 


J 


J 


J 


J 


J 


J 


J 


J 





M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



A format : 

RRC . @ : A MEM , SEA 
RRC. @:A SEA, MEM 



SI SO 1 1 1 m5 m4 1 


DD 


0 1 


1 


m3 


m2 


ml 


m0 


l l l l l l l 






1 


J 


J 


1 


1 




1 1 1 A12 All A10 A9 A8 


A7 


A6 A5 


A4 A3 


A2 


A1 


AO 


1 1 1 1 1 






1 


1 


j 


J 


J 


1 



When DD = 0, dst is memory specified byA<12:0> 
and num is number specified by m<5:0>. 

When DD = 1, dst and num are exchanged. 



Flag status change : z S V C 




Operation size 



B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

When the number of bits to be shifted is 0, dst and the C flag do not change. 
The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 



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RRM dstl , dst2, num : Rotate Right Multi Bit 




Operation : Lower num bits of dst2&dstl «— rotate right lower num bits of dst2 & 

dstl, repeats by the number of num. 

Description : Links the contents of lower num bits of dst2 and dstl, then rotates right 

by the num bits. 

Description figure : 



Instruction format : 



RRM.0 LEA, Reg, #8 
RRM.0 LEA, Reg, LEA 



M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dstl, long addressing mode only 
R<3:0> = dst2 



SI 


so 

1 


0 

1 


, ° 


I 11 . xl 


1 1 M7 

I 1 


M6 


( M5 


M4 
1 1 


M3 


M2 


Ml 


MO 


0 


R3 


R2 


R1 


R0 


. 1 


, 0 , 


1 N7 


, N6 


, N5 


t N4 | 


N3 


£ 


r 


| NO 




J 


J 


J 


J 


J 


J L 


1 


J 


J 







Flag status change : z S V C 




Operation size 



B W D 




Notes : Immediate mode inhibited as dstl addressing mode. 

dst2 always consists of words. The upper bits not used are cleared to zero. 

The lower 3 bits of num are effective when the operation size is byte; the 
lower 4 bits, when the operation size is word/double word. 

When the number of bits to be shifted is 0, dstl does not change, and dst2 is 
cleared to zero. 

operation resuits write in dst2 and then in dstl . 



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% 



TLC5-9000 INSTRUCTION SET MANUAL 

RSF : Reset Sign Flag 

Operation : S <— 0 

Description : Resets the sign flag S to 0. 

Instruction format : 

RSF 



Flag status change : z S V C 





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RVBY dst : Reverse Byte 



Operation : dst «- reverse byte order of dst 
Description : Reverses the byte order of dst. 

Instruction format : 



RVBY.0 LEA 




M<7:0> = dst 



Flag status change : z SVC Operation size : b W D 

_ I _ i - I - I lo lo lo 



Notes : Immediate mode inhibited as dst addressing mode. 

When the operation size is byte, the contents of dst do not change. 



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TOSHIBA TLCS-9000 INSTRUCTION SET MANUAL 

RVF : Reset Overflow Flag 

Operation : V <— 0 

Description : Resets the overflow flag V to 0. 

Instruction format : 

RVF 

Flag status change : z S V C 





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TLCS-9000 INSTRUCTION SET MANUAL 



RZF : Reset Zero Flag 




Operation : Z <— 0 

Description : Resets the zero flag Z to 0. 

Instruction format : 



RZF 




Flag status change : 




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V 

TLCS-9000 INSTRUCTION SET MANUAL 



SBC dst, src : Subtract with Carry Flag 

J 

Operation : dst •♦-dst -src- C 

Description : Subtracts the contents of src and carry flag C from the contents of dst, 

then loads the result in dst. 



Instruction format : 



G format : 

SBC.@:G LEA, #8 
SBC.@:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



SI so 

1 l 


0 . 0 , " , 1 , 1 . 1 , 


M7 M6 


M5 M4 M3 

1 1 l 


M2 Ml M0 


1 0 

1 l 


0 0 110 1 

— 1 1 1 1 1 l 


N7 N6 

1 1 


N5 N4 N3 

1 1 l 


N2 ( N1 ( NO 



A format : 

SBC . @ : A MEM , SEA 
SBC. (3: A SEA, MEM 



s v°. 1 


i 1 ■ 1 i m5 ' m4 


i 1 i dd i 


0 


, ° 


,° 


I m3 


m2 


I m1 


| mO 


1 l °.’ 


A12 ( A11 | A10 | A9 


A8 A7 


A6 


A5 


A4 


A3 


A2 


A1 


| AO 


J 1 L 




J 


J 


J 


J 


J 





When DD = 0, dst is memory specified by A<12:0>; src, by m<5:0>. 
When DD = 1, dst and src are exchanged. 



Flag status change : z S V C 




Operation size 



B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 =11 (quick immediate) in A format allowed only when DD = 0. 

The Z flag is set to 1 when the Z flag = 1 and the operation result = 0; 
otherwise, cleared to zero. 

MSB of sign-extended immediate data must be “0”. If immediate data need to 
be sign-extended and its MSB is “1”, sign-extended bits are all Is, and data 
isn’t expressed in BCD. 

G format and II = 0 ; Byte operation — 00~99 h 

Word or Double Word operation — 00~79H 
A format, DD = 0 and SEA = Quick Imm : 0~7 



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TLCS-9000 INSTRUCTION SET MANUAL 



SBCD dst, src : Subtract Decimal with Carry Flag ^ 

Operation : dst ■*— dst - src - C 

Description : Decimal-subtracts the contents of src and carry flag C from the contents 

of dst, then loads the result in dst. 

Instruction format : 



G format : 

SBCD.@:G 

SBCD.@:G 



LEA, #8 
LEA, LEA 



SI SO 0 0 II 


1 


1 1 M7 


M6 


M5 


M4 


M3 


M2 


Ml 


M0 


1 1 1 1 


1 


1 1 1 


1 


1 


1 


1 


J 


J 


J 


10 0 10 


1 


0 1 N7 


N6 


N5 


N4 


, N3 


, N2 


N1 


NO 


1 1 1 1 — 


J 


J 1 1 


J 


J 


J 


j 


j 


J 


J 



M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



A format : 

SBCD.@:A 

SBCD.@:A 



MEM, SEA 
SEA, MEM 



SI 


, so , 1 


1 1 m5 m4 1 

1 1 1 1 1 


. DD , 


0 


0 

1 


1 1 I m3 


r 2 


ml 
J 


j mO 


0 


0 


1 


A12 All A10 A9 A8 


, A7 , 


A6 


, A5 


1 A4 1 A3 - 




A1 

J 


( A0 




J 


J 


J 1 1 1 1 


J L 




J 



When DD = 0, dst is memory specified byA<12:0> 
and src is memory specified by m<5:0>. 

When DD = 1, dst and src are exchanged. 



Flag status change : z S V C 




Operation size 



: B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 =11 (quick immediate) in A format allowed only when DD = 0. 

The Z flag is set to 1 when the Z flag = 1 and the operation result = 0; 
otherwise, cleared to zero. 

MSB of sign-extended immediate data must be “0”. If immediate data need to 
be sign-extended and its MSB is “1”, sign-extended bits are all Is, and data 
isn’t expressed in BCD. 

G format and 11 = 0 ; Byte operation — 00— 99H 

Word or Double Word operation — 00— 79H 
A format, DD = 0 and SEA = Quick Imm : 0—7 



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’v 



TLCS-9000 INSTRUCTION SET MANUAL 

1 / 

Operation : C ■«— 1 
Description : Sets the carry flag C to 1. 

Instruction format : 




SCF 

Flag status change : 2 S VC 





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TLCS-9000 INSTRUCTION SET MANUAL 



SLA dst. num : Arithmetic Shift Left 



Operation 



C •*- dst < MSB > , dst «- shift left dst, 
dst<LSB> ■*— 0, repeats by the number of num 




Description : Loads the contents of the MSB of dst in carry flag C, shifts the contents 

of dst to the left, then loads 0 in the LSB of dst . Repeats this by the 
number of num. The number of the shift in S format is once only. 



Description figure : 




Instruction format : 



S format : 
SLA.@:S LEA,1 




M<7:0> = dst 



G format : 

SLA.@:G LEA, #8 
SLA. @:G LEA, LEA 



S1 i S0 i 0 i 0 i 11 i 1 i 1 , 1 , M7 , M6 , M5 ( M4 ( M3 ( M2 ( 


Ml M0 


’ 1 ° 1 ’ , 1 , ° 1 1 . 1 l 0 | N7 | "6 | N5 | N4 | N3 1 N2 1 


N1 ( NO 



M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



A format : 

SLA. A MEM, SEA 
SLA. A SEA, MEM 



S1 | 50 , 1 , 1 | 1 | mS , m4 | 1 | DD | 0 | 1 | 1 , m3 [ m2 t ml | mO 
0,1,0 A12A11 A10 | A9 f A8 > A7 [ A6 | A5 f A4 f A3 f A2 | A1 | AO 



When DD = 0, dst is memory specified by A< 12:0> 
and num is number specified by m<5:0>. 

When DD = 1, dst and num are exchanged. 



Flag status change : 




Operation size 



B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format only when DD = 0. 

When the number of bits to be shifted is 0, dst and the C flag do not change. 
The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 



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TLCS-9000 INSTRUCTION SET MANUAL 



SLL dst, num : Loqical Shift Left 





Operation 



C ■*— dst < MSB > , dst *— shift left dst, 
dst<LSB> «— 0, repeats by the number of num 



Description : Loads the contents of the MSB of dst in carry flag C, shifts the contents 

of dst to the left, and loads 0 in the LSB of dst. Repeats this by the 
number of num. The number of the shift in S format is once only. 



Description figure : 




Instruction format : 



S format : 

SLL.@:S LEA,1 



G format : 

SLL.@:GLEA,*8 
SLL.@:G LEA, LEA 



ITT 


, S0 . 


1 


0 


0 


l 1 


| 0 


0 


M7 


M6 


M5 


M4 


M3 


M2 


t M1 


M0 


L_ 


J L 




1 


I , - 






1 -T- 


1 


1 


I 


I 


I 


I 




I I 


M<7:0> 


- 


dst 


























SI 


, so , 


0 


i° 


ii 


1 1 


1 1 


1 

1 


M7 


M6 

1 


M5 


M4 

1 


M3 


M2 

1 


Ml 

1 


M0 

1 


1 


, 0 , 


1 


, i 


( 0 


. 1 


, 0 


, 0 


N7 


N6 


N5 


N4 


N3 


N2 


N1 


t NO 




J L 




j 




J 


J 


J 





J 





J 


1 


J 


J 





M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



A format : 

SLL. A MEM, SEA 
SLL. @:A SEA, MEM 



SI 


AJL 


,1,1 ,m5 | m4 i 1 


i DD , 


0 


1 1 m3 

1 1 1 


m2 

1 


ml 


mO 

1 


0 


0 


0 


A12 All A10 A9 A8 


| A7 f 


A6 


A5 A4 A3 


A2 


f A1 


[ A0 




J 


J 


J 1 1 1 1 






J 1 1 


J 







When DD = 0, dst is memory specified byA<12:0> 
and num is number specified by m<5:0>. 

When DD = 1, dst and num are exchanged. 



Flag status change : z S V C 




Operation size 



B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

When the number of bits to be shifted is 0, dst and the C flag do not change. 
The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 



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TLCS-9000 INSTRUCTION SET MANUAL 



SRA dst, num : Arithmetic Shift Right 




Operation : C dst<LSB>, dst shift right dst, dst < MSB > is unchanged, 

repeats by the number of num 

Description : Loads the contents of the LSB of dst in carry flag C, then shifts the 

contents of dst to the right (MSB is unchanged). Repeats this operation 
by the number of num. The number of the shift in S format is once only. 



Description figure : 



Instruction format : 





MSB 


LSB 




c 


1 




t 





S format : 

SRA.@:S LEA,1 



G format : 

SRA.@:G LEA, #8 
SRA. @:G LEA, LEA 



A format : 

SRA. @ :A MEM, SEA 
SRA . @ : A SEA, MEM 



Flag status change : 



S V°| ’ 1 0 . 0 1 1 1 1 . 1 , M7 , M6 , M5 , 


M4 M3 M2 Ml MO 1 


M<7:0> = dst 


si ,S0, 0 , 0 , II , 1 , 1 , 1 .MJ.MS.MS, 


M4 M3 M2 Ml MO 


I,.,,,, NS, 


N4 N3 N2 N1 NO 


M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 


S, ,50, , , 1 , 1 , m5 , m4 , , ,00, 0 , 1 , 


1 m3 m2 ml mO 
l I l l 


0 ( 1 ( 1 A12A11 1 A10 | A9 | A8 | A7 1 A6 | A5 | 


A4 A3 A2 A1 AO 


When DD = 0, dst is memory specified byA<12:0> 
and num is number specified by m<5:0>. 

When DD = 1, dst and num are exchanged. 

SVC Operation size : g W 


1 

D 





Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

When the number of bits to be shifted is 0, dst and the C flag do not change. 
The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 



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TLCS-9000 INSTRUCTION SET MANUAL 



SRL dst, num 



Operation 



Loaical riaht Shift 



C *- dst < LSB > , dst *- shift right dst, 

dst < MSB > *- 0, repeats by the number of num 



Description : Loads the contents of the LSB of dst in carry flag C, shifts the contents 

of dst to the right, and loads 0 in the MSB of dst. Repeats this by the 
number of num. The number of the shift in S format is once only. 



Description figure : 



Instruction format : 



"n" 



dst 



MSB 



LSB 



S format : 

SRL.@:S LEA,1 



SI SO 10.0 



M<7:0> = dst 



1 M7 M6 M5 M4 M3 M2 Ml MO 



G format 



SRL.0:G LEA, #8 
SRL.@:G LEA, LEA 



SI SO 0 0 . II 



M<7:0> 



N<7:0> 



1 M7 M6 M5 M4 M3 M2 Ml MO 



0 1 1 0 1 0 1 N7 N6.N5 ,N4 ,N3,N2 ,N1 NO 



num When II = 0, immediate data (8 bits, signed) 
When II = 1, long addressing mode 
dst, long addressing mode only 



A format : 

SRL.@:AMEM,SEA 
SRL. A SEA, MEM 



SI. SO . 1 



1 m5.m4. 1 DD. 0 



1 m3 m2 ml. mO 



0 | 0 | 1 A12 All A10 [ A9 | A8 | A7 : A6 { A5 | A4 | A3 | A2 : A1 | AO 

When DD = 0, dst is memory specified by A<12:0> 
and num is number specified by m<5:0>. 

When DD = 1, dst and num are exchanged. 



Flag status change : z S V C Operation size : b W D 



* 0 • 



O O O 



Notes 



Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

When the number of bits to be shifted is 0, dst and the C flag do not change. 
The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 



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TLCS-9000 INSTRUCTION SET MANUAL 



SSF : Set Sign Flag 

Operation : S *- 1 

Description : Sets the sign flag S to 1 . 

Instruction format : 




SSF 

Flag status change : 




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V 



TLCS-9000 INSTRUCTION SET MANUAL 



STCF dst, num : Bit Transfer from Carry Flag 




Operation : dst < num > *-C 

Description : Loads the contents of carry flag C in bit num of dst. 
Instruction format : 



G format : 

STCF.@:G LEA, #8 
STCF.@:G LEA, LEA 

M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



SI SO 0 0 II 1 1 1 M7 


M6 


M5 


M4 


M3 


M2 


Ml 


M0 


1 1 1 1 1 1 1 1 


1 


1 




1 




I 


| 




1 1 0 0 0 1 1 1 N7 


N6 


N5 


N4 


N3 


N2 


N1 


( NO 


1 1 1 1 1 1 1 1 


J 


J 


1 


1 


J 


J 



A format : 

STCF. (? : A MEM, SEA 
STCF. A SEA, MEM 

When DD = 0, dst is memory specified byA<12:0> 
and num is number specified by m<5:0>. 

When DD = 1, dst and num are exchanged. 



SI SO 1 
1 1 


.1,1 ,*,5,0,4, 1 


.DD. 1 


, ° 


, ° 


I m3 


i m2 


i m1 


j mO 


0 , 1 , 1 


A12 All A10 A9 A8 


A7 A6 


A5 


A4 


A3 


A2 


A1 


t AO 


1 1 


J 1 1 1 1 


J 1 


J 


J 


J 


J 


J 





Flag status change : z S V C 




Operation size 



• B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 



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TLCS-9000 INSTRUCTION SET MANUAL 



SUB dst, src : Subtract 




Operation : dst «— dst - src 

Description : Subtracts the contents of src from the contents of dst, then loads the 

result in dst. 

Instruction format : 



S format : 

SUB. @ :S Reg, SEA 

SUB.0:S SEA, Reg When DD = 0, dst is specified by R<3:0> and src by m<5:0>. 

WhenDD = 1, dst and src are exchanged. 




G format : 

SUB.@:G LEA, #8 
SUB. @:G LEA, LEA 



SI . SO . 0 



|| 1 1 1 M7 M6 M5 M4 M3 M2 Ml MO 



0 1 N7 N6 N5 N4.N3.N2 N1. NO 



M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



I format: 

SUB. 0:1 LEA, #16 
SUB.0:I LEA, #32 

• #<31:16> 

t I L J I 1 J I 1 1 L — 1 1 L — J L 

M<7:0> = dst 



o ^ Q ^ Q ^ Q | SS | 0 t 0 | 1 | M7 | M6 t M5 | M4 | M3 | M2 | Ml t MO 

#<15:0> 



A format : 

SUB . 0 : A MEM , SEA 
SUB.0:A SEA, MEM 



SI 


l so l 


1,1,1 , m5 , m4 , 


i |DD| 


0 


i° 


0 

J 


1^1 




ml 
J 


( mO 


0 


ll± 


1 A12 All A10 | A9 ( 


A8| A7 1 


A6 


A5 
J 


A4 
J 


j^L 


A2 
J 




AO 
J 



When DD = 0, dst is memory specified byA<12:0> and src by m<5:0>. 
WhenDD = 1 , dst and src are exchanged. 



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Flag status change : z s v c 




Operation size 



• B W 




Notes : #< 31:16 > in I format is used when the operation size is double word. 

m5m4 = 11 (quick immediate) and m5m4 = 00 (register direct) in S format 
allowed only when DD = 0. 

Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 



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TLCS-9000 INSTRUCTION SET MANUAL 



SUB 3 dst, srcl, src2 : Subtract Trinominal 




Operation : dst <— srcl - src2 

Description : Subtracts the contents of src2 from the contents of srcl, then loads the 

result in dst. 

Instruction format : 



SUB3 . @ Reg, LEA, #8 
SUB3.0 Reg, LEA, LEA 



M<7:0> = src2 When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = srcl, long addressing mode only 
R<3:0> = dst 



SI 


l so 


, ° 


. ° • " - 1 < 1 - 1 


M7 

I 


M6 

1 


M5 


M4 ( M3 


( M2 


Ml 

1 


jMO 


0 


R3 


R2 


R1 RO 0 0,1 


N7 


N6 


, N5 , 


N4 N3 


N2 


N1 
J 


( NO 




J 


J 


l 1 1 1 1 


J 


J 


J ! 


I 1 


J 



Flag status change : z S V C 




Operation size 



B W D 




Notes : Immediate mode inhibited as srcl addressing mode. 



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SVF 



TLCS-9000 INSTRUCTION SET MANUAL 



Set Overflow Fla 




Operation : V «— 1 

Description : Sets the overflow flag V to 1. 

Instruction format : 





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TLCS-9000 INSTRUCTION SET MANUAL 



SWI vec : Software Interrupt 



Operation : Software interrupt specified by vec. 

Description : See interrupt exceptions. 

Remarks : The SWI15 software interrupt can only be used by programs like 

emulators and debuggers using special stack pointers. Cannot be used 
by general-purpose user programs. For general-purpose user programs, 
use SWIO to 14. 

Instruction format : 



SWI vec 




V<3:0> = vec 



Flag status change : z S V C 




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TLC5-9000 INSTRUCTION SET MANUAL 




Operation : Z •*— 1 

Description : Sets the zero flag Z to 1 . 

Instruction format : 



SZF 

Flag status change : z S V C 





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TLCS-9000 INSTRUCTION SET MANUAL 



TJP dst : Table Jump 

Operation : PC<-PC + dst 

Description : Makes a PC relative jump. Adds the contents of dst to the program 

counter (PC), then generates the jump destination address. 

Instruction format : 




TJP.0 LEA 



_Ll!Li 


1 - 1 . 0 - 1 . 1 , 0 .M7M6M5, 


M4 ( 


M3 M2 ( M1 ( M0 



M<7:0> = dst 



Flag status change : z S V C 




Operation size 



B W D 




Notes : LEA specifies the address where the distance to the jump destination is 

stored, rather than the jump destination address itself. 

Immediate mode inhibited as dst addressing mode. 

(RWn++), (~RWn), (RDn++), and (— RDn) in Addressing mode are 
incremented or decremented by operation size. 



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TLCS-9000 INSTRUCTION SET MANUAL 



TSET dst, num : Test and Set Bit 

Operation : Z «— inverted value of dst < num >, dst < num > ■*— 1 

Description : Transfers the inverted value of the bit num of dst to the Z flag. Then 

sets the bit num of dst to “1”. 

Instruction format : 



G format : 

TSET.0:G LEA, #8 
TSET.@:G LEA, LEA 

M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



51,50, ° , 0 , I' , , , 1 , 1 ,M7 


M6 


M5 


M4 


M3 


M2 


Ml 


M0 


1 


I 








| 


| 


1 


1,1110 1 0 0 N7 


N6 


N5 


N4 


N3 


N2 


N1 


( NO 


1 1 1 1 1 1 1 1 


J 


J 


1 


L 




J 


J 



A format : 

TSET.@:A MEM, SEA 
TSET. A SEA, MEM 

When DD = 0, dst is memory specified by A<12:0> and num by 
m<5:0>. 

When DD = 1, dst and num are exchanged. 



SI 


I s0 ! 1 


,1,1 , m5 , m4 , 1 


.DD. 1 


1 1 m3 

1 I I 


I m2 


.mi 


| mO 


0 


jJLil 


A12 All A10 A9 A8 


A7 A6 


A5 A4 A3 


A2 


A1 


| A0 


- 


J 1 1 1 1 


J 1 


J 1 1 


J 


J 





Flag status change : z S V c 




Operation size : b W D 




Notes : Immediate mode inhibited as dst addressing mode. m5m4 = ll (quick 

immediate) in A format allowed only when DD = 0. 

The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 

Bus is locked in the read-modify-write cycle. 



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TST dst : Test Operand 

Operation : CC *— dst test result 

Description : Compares the operand with 0 (dst - 0). Flags are set according to the 

test result. 

Instruction format : 




TST. (3 LEA 



SI 


SO ( 1 ( 0 ! 1 ( 0 ( 1 | 0 | M7 | M6 | M5 | 


M4 M3 

1 l 


M2 

l 


Ml ( MO 



M<7:0> = dst 



Flag status change : z S V C 




Operation size : b W D 




Notes : Immediate mode inhibited as dst addressing mode. 



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V 



TLCS-9000 INSTRUCTION SET MANUAL 

UNLK : Unlink Stack Frame J 

Operation : SP «— R2, R2 *- (SP + ) 

Description : Loads the contents of register R2 in the stack pointer (SP), then pops 

from the stack area the value to update R2. 

Instruction format : 



UNLK 




0 , 


1 

1 


1 

1 


1111110100010 
1 1 1 1 1 1 1 1 1 1 1 1 


Flag status change : 


z 


s 


V 


c 








1 - 









139 





TLCS-9000 INSTRUCTION SET MANUAL 

XOR dst, src : Exclusive OR 

\J 

Operation : dst «- dst XOR src 

Description : Exclusive ORs the contents of dst and src, then loads the result in dst. 
Instruction format : 



TOSHIBA 



S format : 

XOR.@:S Regl ,Reg2 

T<3:0> = dst 
R<3:0> = src 

G format : 

XOR.@:G LEA, #8 
XOR. @:G LEA, LEA 

M<7:0> = src When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = dst, long addressing mode only 



si SO . 0 



1 . 1 , 1 M7 M6 M5.M4 M3 M2 Ml MO 



1 1 



11,0 ,N7 N6.N5.N4 N3.N2 N1 NO 




I format: 

XOR.@:I LEA, #16 
XOR. (3: 1 LEA, #32 



A format : 

XOR . @ : A MEM , SEA 
XOR. @:A SEA, MEM 




M<7:0> = dst 




When DD = 0, dst is memory specified by A< 1 2 : 0 > ; src, by m<5:0>. 
When DD = 1, dst and src are exchanged. 



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TLCS-9000 INSTRUCTION SET MANUAL 



Flag status change : z S V C 




Operation size 



B W D 




Notes : # <31:16> in I format is used when the operation size is double word. 

Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 



* 



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TLCS-9000 INSTRUCTION SET MANUAL 



XORCF src, num : Bit Exclusive OR with Carry Flag 




Operation : C •*— C XOR src < num > 

Description : Exclusive ORs the contents of carry flag C with bit num of src, then 

loads the result in the carry flag. 

Instruction format : 



G format : 

XORCF . @ : G LEA , #8 
XORCF. @:G LEA, LEA 

M<7:0> = num When II = 0, immediate data (8 bits, signed) 

When II = 1, long addressing mode 
N<7:0> = src, long addressing mode only 



SI SO 0 


0 II 1 


1 1 M7 


M6 


M5 


M4 


M3 


M2 


Ml 


MO 


1 1 


1 1 1 


J 1 L_ 1 




1 


1 | 




1 


I 


1 


1 , 1 , 0 


, 0 , 1 , 1 


o 

Z 


N6 


N5 


N4 


N3 


N2 


N1 


NO 


1 1 


J 


J L 




J 


J [ 




J 


J 


J 



A format : 

XORCF. A MEM, SEA 
XORCF. A SEA, MEM 



S1 . S0 . 1 , 1 . 1 . m5 . m4 . 1 


|DD| 1 , 0 


,° 


,m3 


, m2 


ml 


[ mO 


1 1 0 A12 All A10 A9 A8 


A7 A6 A5 


A4 


A3 


A2 


A1 


t AO 


1 1 1 1 1 1 1 


J 1 1 


J 


J 


J 


J 





When DD = 0, src is memory specified by A<12:0> and num is number 
specified by m<5:0>. 

When DD = 1, num and src are exchanged. 



Flag status change : z S V C 




Operation size 



• B W D 




Notes : Immediate mode inhibited as dst addressing mode. 

m5m4 = 11 (quick immediate) in A format allowed only when DD = 0. 

The lower 3 bits of num in G or A format are effective when the operation size 
is byte ; the lower 4bits, when the operation size is word ; the lower 5 bits, 
when the operation size is double word. 



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Instruction execution time (Minimum) 



(Number of clock cycles) 



Instructions 


Format 


Operation size 


/Condition 


Byte 


Word 


Double word 


ABCD 


dst, src 


G 


3 


3 


5 






A 


6 


6 


10 


ADC 


dst, src 


G 


2 


2 


3 






A 


5 


5 


8 


ADD 


dst, src 


S 


1 


i 


2 






G 


2 


2 


3 






1 


2 


2 


3 






A 


5 


5 


8 


ADD3 


dst, srcl, src2 




2 


2 


3 


AND 


dst, src 


S 


i 


1 


2 






G 


2 


2 


3 






1 


2 


2 


3 






A 


5 


5 


8 


ANDCF 


src, num 


G 


4 


4 


5 






A 


6 


6 


9 


BCHG 


dst, num 


s 


i 


i 








G 


3 


3 


4 






A 


5 


5 


8 


BFEX 


dst, src, numl, num2 




5 + [numl/4 + 1] 


3 + [numl/4 + 1) 


3 + (numl/4 + 1] 


BFEXS 


dst, src, numl, num2 




7 + [numl/4 + 1] 


5 + Inuml/4 + 1] 


5 + [numl/4 + 1] 


BFIN 


dst, src, numl, num2 




7 + 2*[num1/4 + 1] 


6 + 2*[num1/4 + 1] 


7 + 2*[num1/4 + 1] 


BRES 


dst, num 


S 


i 


i 


_ 






G 


3 


3 


4 






A 


5 


5 


8 


BSOB 


dst, src 


G 


2 


2 


9 






A 


5 


5 


14 


BSOF 


dst, src 


G 


2 


2 


9 






A 


5 


5 


14 


BS1B 


dst, src 


G 


2 


2 


9 






A 


5 


5 


14 


BS1F 


dst, src 


G 


2 


2 


9 






A 


5 


5 


14 


BSET 


dst, num 


s 


1 


1 








G 


3 


3 


4 






A 


5 


5 


8 


BTST 


src, num 


S 


1 


1 


_ 






G 


3 


3 


4 






A 


5 


5 


8 


CBCD 


dst, src 


G 


3 


3 


5 






A ' 


6 


6 


10 


CHK 


mem, src 


G 


— 


9 


14 






A 


— 


9 


14 


CHKS 


mem, src 


G 


— 


9 


14 






A 


— 


9 


14 


CLR 


dst 




1 


1 


2 


CP 


dst, src 


s 


1 


1 


2 






G 


2 


2 


3 






1 


2 


2 


3 






A 


5 


5 


8 



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Instructions 



CPC dst, src 



CPL dst 



CPSN dst, src, cnts 



CPSZ dst, src, cnts 



DIV dst, src 



DIVS dst, src 



DJNZ dst, disp 



DJNZC dst, cond, disp 



dstl, dst2 



EXTS 



EXTZ 



JP 



LD 



dst 



dst 



dst 



dst, src 



LDA dst, src 



LDCF src, num 



LDS 



MAC 



MACS 



MAX 



dst, src, cnts 



dst, src1,src2 



dst, src1,src2 



dst, src 



MAXS dst, src 



MIN 



dst, src 



MINS dst, src 



MIRR dst 



MUL dst, src 



MULS dst', src 



NEG dst 



OR dst, src 



Format 

/Condition 



G 

A 



Byte 



2 

5 



Operation size 

Word 

2 

5 



Double word 




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Instructions 


Format 


1 Operation size 1 




/Condition 


Byte 


Word 


Doubleword 


lORCF 


src # num 


G 

A 


4 

6 


4 

6 




5 

9 




[pop 


dst 




5 


5 


— 

8 


[push 


src 




5 


5 


7 


(PUSHA 


dst 




— 


6 


9 


RL 


dst, num 


S 


1 


1 




2 


— 






G 

A 


3 + [n/4] 
5 + [n/4] 


3 + [n/4] 
5 + [n/4] 


3 + [n/4] 
7 + [n/4] 


RLC 


dst, num 


S 

G 

A 


1 

3 + [n/4] 
5 + [n/4] 


1 

3 + [n/4] 
5 + [n/4] 


3 + 
7 + 


2 

n/4] 

n/4] 


RLM 


dstl, dst2, num 




7 + [n/4] 


7 + [n/4] 


1 8 + [n/4] 1 


RR 


dst, num 


S 


1 


1 




2 








G 

A 


3 + [n/4] 
5 + [n/4] 


3 + [n/4] 
5 + [n/4] 


3 + [n/4’ 
7 + [n/4; 




RRC 


dst, num 


S 

G 

A 


1 

3 + [n/4] 
5 + [n/4] 


1 

3 + [n/4] 
5 + [n/4] 


• 

3 + 
7 + 


i 

[n/4] 

[n/4] 


[rrm 


dstl, dst2, num 




7 + Jn/4] 


7 + [n/4] 


8 + [n/4] 


|rvby 


dst 




i 


1 


3 


SBC 


dst, src 


G 

A 


2 

5 


2 

5 


3 

8 


jSBCD 


dst, src 


G 

A 


3 

6 


3 

6 


5 

10 




SLA 


dst, num 


S 

G 

A 


1 

3 + [n/4] 
5 + [n/4] 




2 

3 + [n/4] 
7 + [n/4] 




ISLL 


dst, num 


S 

G 

A 


1 

3 + [n/4] 
5 + [n/4] 




2 

3 + [n/4] 
7 + [n/4] 


jSRA 


dst, num 


S 

G 

A 


i 

3 + [n/4] 
5 + [n/4] 




2 

3 + [n/4] 
7 + [n/4] 




SRL 


dst, num 


S 

G 

A 


1 

3 + [n/4] 
5 + [n/4] 


i 

3 + [n/4] 
5 + [n/4] 


2 

3 + [n/4] 
7 + [n/4] 




JsTCF 


dst, num 


G 

A 


4 

6 


4 

6 


c 

m 

c 

m 


t 

1 




SUB 


dst, src 


s 

G 

1 

A 


1 

• 2 

2 
5 


1 

2 
2 
5 


2 

3 

3 

8 


SUB3 


dst, srcl, src2 




2 


2 


3 


TJP 


dsf 




— 


5 


6 


TSET 


dst, num 


G 

A 


4 

7 


4 

7 


6 

11 


TST 


dst 




1 


i 


2 


IxOR 


dst, src 


s 

G 

1 

A 


1 

2 
2 
5 


1 

2 
2 
5 


2 

3 

3 

8 



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TLCS-9000 INSTRUCTION SET MANUAL 





Format 




Operation size 




insxruciions 


/Condition 


Byte 


Word 


Double word 


XORCF src, num 


G 


4 


4 


5 




A 


6 


6 


9 



Notes : [numl/4 + 1] is a value obtained by dividing the number of shifted bits by 4 and rounding up to an 

integer. 

[n/4] is a value obtained by dividing the number of shifted bits by 4 and rounding up to an integer. 



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(Number of clock cycles) 



Instructions 


Condition 


JRC cond,disp 


True 

False 


JRBC num, abs, disp 


True 

False 


JRBS num, abs, disp 


True 

False 




(Number of clock cycles) 



Instructions 


1 SP 




16BIT 


32BIT 


CALL dst 


11 


12 


CALR disp 


10 


11 


LINK disp 


5 


6 


RET 


8 


9 


RETD disp 


8 


9 


UNLK 


5 


9 




(Number of clock cycles) 



Instructions 


Banks 


Memory stacks 


RETI 


12 


17 


RETS 


12 


17 


SWI vec 


18 


25 




(Number of clock cycles)